Signal Pins
2.2 Signal Pins
After reset, each pin is configured for its primary function (listed first). In the 56F8122, after reset, each
pin must be configured for the desired function. The initialization software will configure each pin for the
function listed first for each pin, as shown in Table 2-2. Any alternate functionality must be programmed.
Note: Signals in italics are not available in the 56F8122 device.
If the “State During Reset” lists more than one state for a pin, the first state is the actual reset state. Other
states show the reset condition of the alternate function, which you get if the alternate pin function is
selected without changing the configuration of the alternate peripheral. For example, the SCLK0/GPIOB3
pin shows that it is tri-stated during reset. If the GPIOB_PER is changed to select the GPIO function of
the pin, it will become an input if no other registers are changed.
Table 2-2 Signal and Package Information for the 48-Pin LQFP
StateDuring
Signal Name
Pin No.
Type
Signal Description
Reset
VDD_IO
VDD_IO
5
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O interface
and also the Processor core throught the on-chip voltage regulator, if
it is enabled.
14
34
44
30
VDD_IO
VDD_IO
VDDA_ADC
Supply
Supply
ADC Power — This pin supplies 3.3V power to the ADC modules. It
must be connected to a clean analog power supply.
VSS
VSS
10
13
31
45
29
Ground — These pins provide ground for chip logic and I/O drivers.
VSS
VSS
VSSA_ADC
Supply
Supply
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
VCAP
VCAP
1
2
43
17
Supply
VCAP1 - 2 — Connect each pin to a 2.2μF or greater bypass capacitor
in order to bypass the core logic voltage regulator, required for proper
chip operation.
56F8322 Technical Data, Rev. 16
Freescale Semiconductor
Preliminary
19
FREESCALE [ Freescale ]
