Part 1 Overview
1.1 56F803 Features
1.1.1
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Processing Core
Efficient 16-bit 56800 family controller engine with dual Harvard architecture
As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
Single-cycle 16
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16
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bit parallel Multiplier-Accumulator (MAC)
Two 36
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bit accumulators, including extension bits
16
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bit bidirectional barrel shifter
Parallel instruction set with unique processor addressing modes
Hardware DO and REP loops
Three internal address buses and one external address bus
Four internal data buses and one external data bus
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/OnCE debug programming interface
1.1.2
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Memory
Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
On-chip memory including a low-cost, high-volume Flash solution
— 31.5K
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16-bit words of Program Flash
— 512K
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16
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bit words of Program RAM
— 4K
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16
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bit words of Data Flash
— 2K
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16
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bit words of Data RAM
— 2K
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16
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bit words of Boot Flash
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Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K
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16 bits of Data memory
— As much as 64K
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16 bits of Program memory
1.1.3
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Peripheral Circuits for 56F803
Pulse Width Modulator module (PWM) with six PWM outputs, three Current Sense inputs, and three Fault
inputs, fault-tolerant design with dead time insertion, supports both center- and edge- aligned modes,
supports Freescale’s patented dead time distortion correction
Two 12
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bit Analog-to-Digital Converters (ADCs), which support two simultaneous conversions; ADC and
PWM modules can be synchronized
Quadrature Decoder with four inputs (shares pins with Quad Timer)
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56F803 Technical Data, Rev. 16
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Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
