Register Descriptions
6.3 Register Descriptions
A write to an address without an associated register is an NOP. A read from an address without an
associated register returns unknown data.
Table 6-1 SIM Registers (SIM_BASE = $00 F100)
Register
Acronym
Section
Location
Base Address +
Register Name
CTRL
$0
$1
$2
$3
$4
$5
$6
$7
$8
Control Register
6.3.1
6.3.2
6.3.3
6.3.3
6.3.3
6.3.3
6.3.4
6.3.5
6.3.6
RSTAT
SWC0
SWC1
SWC2
SWC3
MSHID
LSHID
PWR
Reset Status Register
Software Control Register 0
Software Control Register 1
Software Control Register 2
Software Control Register 3
Most Significant Half of JTAG ID
Least Significant Half of JTAG ID
Power Control Register
Reserved
CLKOUT
PCR
$A
$B
CLKO Select Register
6.3.7
6.3.8
Peripheral Clock Rate Register
PCE0
PCE1
SD0
$C
Peripheral Clock Enable Register 0
Peripheral Clock Enable Register 0
Stop Disable Register 0
6.3.9
$D
6.3.10
6.3.11
6.3.12
6.3.13
6.3.14
6.3.15
6.3.16
6.3.17
6.3.18
6.3.19
6.3.20
6.3.21
6.3.22
6.3.23
$E
SD1
$F
Stop Disable Register 1
IOSAHI
IOSALO
PROT
GPSA0
GPSA1
GPSB0
GPSB1
GPSCD
IPS0
$10
$11
$12
$13
$14
$15
$16
$17
$18
$19
$1A
I/O Short Address Location High Register
I/O Short Address Location Low Register
Protection Register
GPIO Peripheral Select Register 0 for GPIOA
GPIO Peripheral Select Register 1 for GPIOA
GPIO Peripheral Select Register 0 for GPIOB
GPIO Peripheral Select Register 1 for GPIOB
GPIO Peripheral Select Register for GPIOC and GPIOD
Internal Peripheral Source Select Register 0 for PWM
Internal Peripheral Source Select Register 1 for DACs
Internal Peripheral Source Select Register 2 for Quad Timer A
Reserved
IPS1
IPS2
56F8037/56F8027 Data Sheet, Rev. 6
Freescale Semiconductor
95
FREESCALE [ Freescale ]
