Phase Locked Loop Timing
10.6 Phase Locked Loop Timing
Table 10-11 PLL Timing
Characteristic
Symbol
fosc
Min
4
Typ
8
Max
—
Unit
MHz
MHz
MHz
µs
External reference crystal frequency for the PLL1
Internal reference relaxation oscillator frequency for the PLL
frosc
fop
—
96
—
—
—
8
—
PLL output frequency2 (24 x reference frequency)
PLL lock time3
192
40
—
—
tplls
100
0.37
—
Accumulated jitter using an 8MHz external crystal as the PLL source4
Cycle-to-cycle jitter
JA
%
tjitterpll
350
ps
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL
is optimized for 8MHz input.
2. The core system clock will operate at 1/6 of the PLL output frequency.
3. This is the time required after the PLL is enabled to ensure reliable operation.
4. This is measured on the CLKO signal (programmed as System clock) over 264 System clocks at 32MHz System clock frequency
and using an 8MHz oscillator frequency.
10.7 Relaxation Oscillator Timing
Table 10-12 Relaxation Oscillator Timing
Characteristic
Symbol
Minimum
Typical
Maximum
Unit
Relaxation Oscillator output frequency1
Normal Mode
Standby Mode
fop
—
—
8.05
200
MHz
kHz
Relaxation Oscillator stabilization time2
troscs
—
—
1
3
ms
ps
Cycle-to-cycle jitter. This is measured on the CLKO
signal (programmed prescaler_clock) over 264 clocks3
tjitterrosc
400
—
Minimum tuning step size
Maximum tuning step size
—
—
—
.08
40
—
—
%
%
%
Variation over temperature -40°C to 150ºC4
+1.0 to -1.5 +3.0 to -3.0
0 to +1 +2.0 to -2.0
Variation over temperature 0°C to 105ºC4
—
%
1. Output frequency after factory trim.
2. This is the time required from Standby to Normal mode transition.
3. JA is required to meet QSCI requirements.
4. See Figure 10-5
56F8037/56F8027 Data Sheet, Rev. 6
Freescale Semiconductor
149
FREESCALE [ Freescale ]
