Clocks
EXTENDED_POR
JTAG
POR
pulse shaper
Power-On
Reset
(active low)
Memory
Subsystem
Delay 64
OSC_CLK
Clock
CLKGEN_RST
OCCS
COMBINED_RST
External
RESET IN
(active low)
PERIP_RST
Delay 32
OSC_CLK
Clock
RESET
Peripherals
pulse shaper
Delay 32
COP_TOR
(active low)
sys clocks
SW Reset
56800E
pulse shaper
Delay 32
sys clocks
COP_LOR
(active low)
pulse shaper
Delay blocks assert immediately and
deassert only after the programmed
number of clock cycles.
CORE_RST
Figure 6-28 Sources of RESET Functional Diagram (Test modes not included)
POR resets are extended 64 OSC_CLK clocks to stabilize the power supply and clock source. All resets
are subsequently extended for an additional 32 OSC_CLK clocks and 64 system clocks as the various
internal reset controls are released. Given the normal relaxation oscillator rate of 8MHz, the duration of a
POR reset from when power comes on to when code is running is 28µS. An external reset generation
circuit may also be used. A description of how these resets are used to initialize the clocking system and
system modules is included in Section 6.7.
6.7 Clocks
The memory, peripheral and core clocks all operate at the same frequency (32MHz maximum) with the
exception of the peripheral clocks for quad timers TMRA and TMRB and the PWM, which have the option
to operate at 3X system clock. The SIM is responsible for clock distributions.
While the SIM generates the ADC peripheral clock in the same way it generates all other peripheral clocks,
the ADC standby and conversion clocks are generated by a direct interface between the ADC and the
OCCS module.
56F8037/56F8027 Data Sheet, Rev. 6
Freescale Semiconductor
127
FREESCALE [ Freescale ]
