56F8035/56F8025 Data Sheet Table of Contents
7.3
Product Analysis. . . . . . . . . . . . . . . . . . 114
Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
1.3
56F8035/56F8025 Features . . . . . . . . . . . 6
56F8035/56F8025 Description . . . . . . . . . 8
Award-Winning Development
Part 8 General-Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . .114
Environment . . . . . . . . . . . . . . . . . . . 9
Architecture Block Diagram . . . . . . . . . . . 9
Product Documentation . . . . . . . . . . . . . 17
Data Sheet Conventions. . . . . . . . . . . . . 17
8.1
8.2
8.3
Introduction. . . . . . . . . . . . . . . . . . . . . . 114
Configuration . . . . . . . . . . . . . . . . . . . . 114
Reset Values . . . . . . . . . . . . . . . . . . . . 117
1.4
1.5
1.6
Part 9 Joint Test Action Group (JTAG) . . .122
Part 2 Signal/Connection Descriptions . . . 18
9.1
56F8035/56F8025 Information . . . . . . . 122
2.1
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . 18
56F8035/56F8025 Signal Pins . . . . . . . . 22
Part 10Specifications. . . . . . . . . . . . . . . . . .122
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
General Characteristics . . . . . . . . . . . . 122
DC Electrical Characteristics . . . . . . . . 126
AC Electrical Characteristics . . . . . . . . 129
Flash Memory Characteristics . . . . . . . 130
External Clock Operation Timing . . . . . 130
Phase Locked Loop Timing . . . . . . . . . 131
Relaxation Oscillator Timing. . . . . . . . . 132
Reset, Stop, Wait, Mode Select, and
Part 3 OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Overview. . . . . . . . . . . . . . . . . . . . . . . . . 33
Features . . . . . . . . . . . . . . . . . . . . . . . . . 33
Operating Modes . . . . . . . . . . . . . . . . . . 33
Internal Clock Source . . . . . . . . . . . . . . . 34
Crystal Oscillator. . . . . . . . . . . . . . . . . . . 34
Ceramic Resonator. . . . . . . . . . . . . . . . . 35
External Clock Input - Crystal Oscillator
Option. . . . . . . . . . . . . . . . . . . . . . . 35
Interrupt Timing . . . . . . . . . . . . . . 133
Serial Peripheral Interface (SPI)
10.9
3.8
Alternate External Clock Input . . . . . . . . 36
Timing . . . . . . . . . . . . . . . . . . . . . 134
10.10 Quad Timer Timing. . . . . . . . . . . . . . . . 138
10.11 Serial Communication Interface (SCI)
Timing . . . . . . . . . . . . . . . . . . . . . 140
10.12 Inter-Integrated Circuit Interface (I2C)
Timing . . . . . . . . . . . . . . . . . . . . . 141
10.13 JTAG Timing. . . . . . . . . . . . . . . . . . . . . 143
10.14 Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . . 144
Part 4 Memory Maps. . . . . . . . . . . . . . . . . . . 36
4.1
4.2
4.3
4.4
4.5
4.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . 36
Interrupt Vector Table . . . . . . . . . . . . . . . 37
Program Map . . . . . . . . . . . . . . . . . . . . . 39
Data Map . . . . . . . . . . . . . . . . . . . . . . . . 39
EOnCE Memory Map . . . . . . . . . . . . . . . 41
Peripheral Memory-Mapped Registers . . 42
10.15 Equivalent Circuit for ADC Inputs. . . . . 145
10.16 Comparator (CMP) Parameters . . . . . . 146
10.17 Digital-to-Analog Converter (DAC)
Parameters . . . . . . . . . . . . . . . . . 146
Part 5 Interrupt Controller (ITCN) . . . . . . . . 56
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . 56
Features . . . . . . . . . . . . . . . . . . . . . . . . . 56
Functional Description . . . . . . . . . . . . . . 56
Block Diagram. . . . . . . . . . . . . . . . . . . . . 59
Operating Modes . . . . . . . . . . . . . . . . . . 59
Register Descriptions . . . . . . . . . . . . . . . 59
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.18 Power Consumption . . . . . . . . . . . . . . . 148
Part 11Packaging . . . . . . . . . . . . . . . . . . . . .149
11.1
56F8035/56F8025 Package and
Pin-Out Information . . . . . . . . . . . 149
Part 6 System Integration Module (SIM). . . 79
Part 12Design Considerations . . . . . . . . . .155
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . 79
Features . . . . . . . . . . . . . . . . . . . . . . . . . 80
Register Descriptions . . . . . . . . . . . . . . . 81
Clock Generation Overview . . . . . . . . . 106
Power-Saving Modes . . . . . . . . . . . . . . 108
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . 109
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . 112
12.1
12.2
Thermal Design Considerations . . . . . . 155
Electrical Design Considerations . . . . . 156
Part 13Ordering Information . . . . . . . . . . . .157
Part 14Appendix. . . . . . . . . . . . . . . . . . . . . .158
Part 7 Security Features. . . . . . . . . . . . . . . 112
7.1
7.2
Operation with Security Enabled. . . . . . 112
Flash Access Lock and Unlock
Mechanisms. . . . . . . . . . . . . . . . . 113
56F8035/56F8025 Data Sheet, Rev. 6
Freescale Semiconductor
5
FREESCALE [ Freescale ]
