Introduction
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F8025 are organized into functional groups, as detailed in Table 2-1.
Table 2-2 summarizes all device pins. In Table 2-2, each table row describes the signal or signals present
on a pin, sorted by pin number.
Table 2-1 Functional Group Pin Allocations
Functional Group
Power Inputs (VDD, VDDA
Number of Pins
)
3
4
Ground (VSS, VSSA
Supply Capacitors
Reset1
)
2
1
Pulse Width Modulator (PWM) Ports1
Serial Peripheral Interface (SPI) Ports1
Timer Module A (TMRA) Ports1
12
4
4
Analog-to-Digital Converter (ADC) Ports1
Serial Communications Interface 0 (SCI0) Ports1
Inter-Integrated Circuit Interface (I2C) Ports1
Oscillator Signals1
8
2
2
2
JTAG/Enhanced On-Chip Emulation (EOnCE)1
4
1. Pins may be shared with other peripherals; see Table 2-2.
56F8025 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
17
FREESCALE [ Freescale ]
