56F8025 Signal Pins
2.2 56F8025 Signal Pins
After reset, each pin is configured for its primary function (listed first). Any alternate functionality must
be programmed.
Table 2-3 56F8025 Signal and Package Information for the 44-Pin LQFP
Signal
Name
LQFP
Pin No.
StateDuring
Reset
Type
Signal Description
VDD
VDD
VSS
29
35
17
28
36
11
Supply
Supply
I/O Power — This pin supplies 3.3V power to the chip I/O interface.
Supply
Supply
VSS — These pins provide ground for chip logic and I/O drivers.
VSS
VSS
VDDA
Supply
Supply
Supply
Supply
Supply
Supply
ADC Power — This pin supplies 3.3V power to the ADC modules. It
must be connected to a clean analog power supply.
VSSA
12
ADC Analog Ground — This pin supplies an analog ground to the
ADC modules.
VCAP
VCAP
18
34
21
VCAP — Connect this pin to a 4.7μF or greater bypass capacitor in
order to bypass the core voltage regulator, required for proper chip
operation. See Section 10.2.1.
RESET
Input
Input,
internal
pull-up
enabled
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the chip is initialized and placed in the
reset state. A Schmitt trigger input is used for noise immunity. The
internal reset signal will be deasserted synchronous with the internal
clocks after a fixed number of internal clocks.
(GPIOA7)
Input/Open
Drain
Output
Port A GPIO — This GPIO pin can be individually programmed as
an input or open drain output pin. Note that RESET functionality is
disabled in this mode and the chip can only be reset via POR, COP
reset, or software reset.
After reset, the default state is RESET.
Return to Table 2-2
56F8025 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
21
FREESCALE [ Freescale ]
