56F8023 General Description
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 32KB (16K x 16) Program Flash
• 4KB (2K x 16) Unified Data/Program RAM
• One 6-channel PWM module
• Two 3-channel 12-bit Analog-to-Digital Converters
(ADCs)
• Two Internal 12-bit Digital-to-Analog Converters
(DACs)
• Two Analog Comparators
• One Programmable Interval Timer (PIT)
• One Queued Serial Communication Interface (QSCI)
with LIN slave functionality
• One Queued Serial Peripheral Interfaces (QSPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I
2
C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage
Interrupt (LVI) Module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 26 GPIO lines
• 32-pin LQFP Package
RESET or
GPIOA
4
JTAG/EOnCE
Port or
GPIOD
V
CAP
V
DD
V
SS
2
V
DDA
V
SSA
5
Digital Reg
Analog Reg
PWM
or TMRA or GPIOA
Program Controller
and Hardware
Looping Unit
16-Bit
56800E Core
Low-Voltage
Supervisor
Bit
Manipulation
Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
DAC
4
PAB
PDB
CDBR
CDBW
AD0
ADC
or CMP
or GPIOC
Memory
Program Memory
16K x 16 Flash
Unified Data /
Program RAM
2K x 16
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
4
AD1
System Bus
Control
Programmable
Interval
Timer
IPBus Bridge (IPBB)
I
2
C
or CMP
or GPIOB
QSPI
or PWM
or I
2
C
or TMRA
or GPIOB
4
QSCI
or PWM
or I
2
C
or TMRA
or GPIOB
2
COP/
Watchdog
Interrupt
Controller
System
Integration
Module
P
O
R
O
Clock
S
Generator*
C
2
*Includes On-Chip
Relaxation Oscillator
56F8023 Block Diagram
56F8023 Data Sheet, Rev. 3
Freescale Semiconductor
Preliminary
3
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
