Register Descriptions
Add.
Address
Offset Acronym
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
R
0
0
0
0
SIM_
CTRL
TC3_ TC2_ TC1_ TC0_
SCI_
SD
TC3_
INP
ONCE SW
EBL0 RST
STOP_
DISABLE
WAIT_
DISABLE
$0
SD
0
SD
0
SD
0
SD
0
0
0
0
0
0
0
0
0
SIM_
$1
SWR COPR EXTR POR
RSTAT
W
R
$2
$3
$4
$5
$6
$7
$8
SIM_SWC0
SIM_SWC1
SIM_SWC2
SIM_SWC3
SIM_MSHID
SIM_LSHID
Software Control Data 0
Software Control Data 1
Software Control Data 2
Software Control Data 3
W
R
W
R
W
R
W
R
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
0
1
W
R
W
R
SIM_PWR
Reserved
LRSTDBY
W
R
W
R
0
0
0
0
0
0
0
0
0
0
SIM_
CLKOUT
CLK
DIS
$A
$B
$C
PWM3 PWM2 PWM1 PWM0
CLKOSEL
CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_ CFG_
B7
SIM_GPS
SIM_PCE
TCR
PCR
0
CFG_A5
CFG_A4
0
B6
B5
B4
B3
B2
B1
B0
W
R
0
0
0
0
0
0
0
0
I2C
0
ADC
0
TMR
0
SCI
0
SPI
0
PWM
W
R
0
0
1
0
0
0
0
0
$D SIM_IOSAHI
$E SIM_IOSALO
ISAL[23:22]
W
R
ISAL[21:6]
W
0
= Read as 0
= Reserved
= Read as 1
= Reserved
Figure 6-1 SIM Register Map Summary
6.3.1
SIM Control Register (SIM_CTRL)
Base + $0
Read
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
TC3_ TC2_ TC1_ TC0_ SCI_
SD
TC3_
INP
ONCE SW
EBL
STOP_
DISABLE
WAIT_
DISABLE
SD
SD
SD
SD
RST
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-2 SIM Control Register (SIM_CTRL)
6.3.1.1
Timer Channel 3 Stop Disable (TC3_SD)—Bit 15
This bit enables the operation of the Timer Channel 3 peripheral clock in Stop mode.
•
0 = Timer Channel 3 disabled in Stop mode
56F8013/56F8011 Data Sheet, Rev. 12
Freescale Semiconductor
67
FREESCALE [ Freescale ]
