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    56853 参数 Datasheet PDF下载

    56853图片预览
    型号： 56853
    PDF下载： 下载PDF文件 查看货源
    内容描述： 16位数字信号控制器 [16-bit Digital Signal Controllers]
    分类和应用： 控制器
    文件页数/大小： 60 页 / 1339 K
    品牌： FREESCALE [ Freescale ]
     浏览型号56853的Datasheet PDF文件第1页浏览型号56853的Datasheet PDF文件第3页浏览型号56853的Datasheet PDF文件第4页浏览型号56853的Datasheet PDF文件第5页浏览型号56853的Datasheet PDF文件第6页浏览型号56853的Datasheet PDF文件第7页浏览型号56853的Datasheet PDF文件第8页浏览型号56853的Datasheet PDF文件第9页  
    56853 General Description  
    • 120 MIPS at 120MHz  
    • Serial Port Interface (SPI)  
    • 12K x 16-bit Program SRAM  
    • 4K x 16-bit Data SRAM  
    • 1K x 16-bit Boot ROM  
    • 8-bit Parallel Host Interface  
    • General Purpose 16-bit Quad Timer  
    • JTAG/Enhanced On-Chip Emulation (OnCE™) for  
    unobtrusive, real-time debugging  
    • Access up to 2M words of program memory or 8M of  
    data memory  
    • Computer Operating Properly (COP)/Watchdog Timer  
    • Time-of-Day (TOD)  
    • Chip Select Logic for glue-less interface to ROM and  
    SRAM  
    • 128 LQFP package  
    • Six (6) independent channels of DMA  
    • Up to 41 GPIO  
    • Enhanced Synchronous Serial Interfaces (ESSI)  
    • Two (2) Serial Communication Interfaces (SCI)  
    V
    V
    6
    V
    V
    SSA  
    V
    V
    SSIO  
    SS  
    DDA  
    DDIO  
    DD  
    6
    10  
    11  
    6
    JTAG/  
    Enhanced  
    OnCE  
    16-Bit  
    56800E Core  
    Program Controller  
    and  
    Hardware Looping Unit  
    Address  
    Generation Unit  
    Data ALU  
    Bit  
    16 x 16 + 36 → 36-Bit MAC  
    Three 16-bit Input Registers  
    Four 36-bit Accumulators  
    Manipulation  
    Unit  
    PAB  
    PDB  
    CDBR  
    CDBW  
    Memory  
    XDB2  
    Program Memory  
    XAB1  
    12,288 x 16 SRAM  
    XAB2  
    System Bus  
    Control  
    DMA  
    6 channel  
    Boot ROM  
    PAB  
    1024 x 16 ROM  
    PDB  
    Data Memory  
    4,096 x 16 SRAM  
    CDBR  
    CDBW  
    IPBus Bridge (IPBB)  
    Decoding  
    Peripherals  
    POR  
    CLKO  
    IPBus CLK  
    3
    MODEA-C or  
    (GPIOH0-H2)  
    System  
    Integration  
    Module  
    COP/TOD CLK  
    RSTO  
    External Address  
    Bus Switch  
    A0-20 [20:0]  
    RESET  
    External Data  
    Bus Switch  
    External Bus  
    Interface Unit  
    D0-D15 [15:0]  
    EXTAL  
    XTAL  
    Clock  
    Generator  
    ESSI0  
    or  
    GPIOC  
    2 SCI  
    or  
    GPIOE  
    Quad  
    Timer  
    or  
    SPI  
    or  
    GPIOF  
    Host  
    Interrupt  
    COP/  
    Watch-  
    dog  
    Time  
    of  
    Day  
    RD Enable  
    WR Enable  
    Interface Controller  
    or  
    GPIOB  
    Bus Control  
    OSC PLL  
    GPIOG  
    CS0-CS3[3:0] or  
    GPIOA0-A3[3:0]  
    6
    4
    4
    4
    16  
    IRQA  
    IRQB  
    56853 Block Diagram  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    3
    Part 1 Overview  
    1.1 56853 Features  
    1.1.1  
    Core  
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    •
    Efficient 16-bit engine with dual Harvard architecture  
    120 Million Instructions Per Second (MIPS) at 120MHz core frequency  
    Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)  
    Four (4) 36-bit accumulators including extension bits  
    16-bit bidirectional shifter  
    Parallel instruction set with unique DSP addressing modes  
    Hardware DO and REP loops  
    Three (3) internal address buses and one (1) external address bus  
    Four (4) internal data buses and one (1) external data bus  
    Instruction set supports both DSP and controller functions  
    Four (4) hardware interrupt levels  
    Five (5) software interrupt levels  
    Controller-style addressing modes and instructions for compact code  
    Efficient C Compiler and local variable support  
    Software subroutine and interrupt stack with depth limited only by memory  
    JTAG/Enhanced OnCE debug programming interface  
    1.1.2  
    Memory  
    •
    Harvard architecture permits up to three (3) simultaneous accesses to program and data memory  
    •
    On-Chip Memory  
    — 12K × 16-bit Program SRAM  
    — 4K × 16-bit Data SRAM  
    — 1K × 16-bit Boot ROM  
    •
    Off-Chip Memory Expansion (EMI)  
    — Access up to 2M words of program memory or 8M data memory  
    — Chip Select Logic for glue-less interface to ROM and SRAM  
    1.1.3  
    Peripheral Circuits for 56853  
    General Purpose 16-bit Quad Timer*  
    •
    •
    •
    •
    •
    Two (2) Serial Communication Interfaces (SCI)*  
    Serial Peripheral Interface (SPI) Port*  
    Enhanced Synchronous Serial Interface (ESSI) modules*  
    Computer Operating Properly (COP)  
    56853 Technical Data, Rev. 6  
    4
    Freescale Semiconductor  
    56853 Description  
    •
    •
    •
    •
    •
    •
    •
    Watchdog Timer  
    JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, real-time debugging  
    Six (6) independent channels of DMA  
    8-bit Parallel Host Interface*  
    Time-of-Day (TOD)  
    128 LQFP package  
    Up to 41 GPIO  
    * Each peripheral I/O can be used alternately as a General Purpose I/O if not needed  
    1.1.4  
    Energy Information  
    •
    Fabricated in high-density CMOS with 3.3V, TTL-compatible digital inputs  
    •
    Wait and Stop modes available  
    1.2 56853 Description  
    The 56853 is a member of the 56800E core-based family of controllers. It combines, on a single chip, the  
    processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a  
    flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,  
    configuration flexibility, and compact program code, the 56853 is well-suited for many applications. The  
    56853 includes many peripherals that are especially useful for low-end Internet appliance applications  
    and low-end client applications such as telephony; portable devices; Internet audio and point-of-sale  
    systems, such as noise suppression; ID tag readers; sonic/subsonic detectors; security access devices;  
    remote metering; sonic alarms.  
    The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in  
    parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming  
    model and optimized instruction set allow straightforward generation of efficient, compact DSP and  
    control code. The instruction set is also highly efficient for C Compilers, enabling rapid development of  
    optimized control applications.  
    The 56853 supports program execution from either internal or external memories. Two data operands can  
    be accessed from the on-chip Data RAM per instruction cycle. The 56853 also provides two external  
    dedicated interrupt lines, and up to 41 General Purpose Input/Output (GPIO) lines, depending on  
    peripheral configuration.  
    The 56853 controller includes 12K words of Program RAM, 4K words of Data RAM, and 1K words of  
    Boot ROM. It also supports program execution from external memory. The 56800 core can access two data  
    operands from the on-chip Data RAM per instruction cycle.  
    This controller also provides a full set of standard programmable peripherals that include an 8-bit parallel  
    Host Interface, Enhanced Synchronous Serial Interface (ESSI), one Serial Peripheral Interface (SPI), the  
    option to select a second SPI or two Serial Communications Interfaces (SCIs), and Quad Timer. The Host  
    Interface, ESSI, SPI, SCI, four chip selects and quad timer can be used as General Purpose Input/Outputs  
    (GPIOs) if its primary function is not required.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    5
    1.3 State of the Art Development Environment  
    •
    Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use  
    component-based software application creation with an expert knowledge system.  
    •
    The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,  
    compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards  
    will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable  
    tools solution for easy, fast, and efficient development.  
    1.4 Product Documentation  
    The four documents listed in Table 1-1 are required for a complete description of and proper design with  
    the 56853. Documentation is available from local Freescale distributors, Freescale Semiconductor sales  
    offices, Freescale Literature Distribution Centers, or online at www.freescale.com.  
    Table 1-1 56853 Chip Documentation  
    Topic  
    DSP56800E  
    Description  
    Order Number  
    DSP56800ERM  
    Detailed description of the 56800E architecture, 16-bit  
    controller core processor and the instruction set  
    Reference Manual  
    DSP56853  
    User’s Manual  
    Detailed description of memory, peripherals, and  
    interfaces of the 56853  
    DSP5685xUM  
    DSP56853  
    DSP56853  
    Technical Data Sheet  
    Electrical and timing specifications, pin descriptions,  
    and package descriptions  
    DSP56853  
    Errata  
    Details any chip issues that might be present  
    DSP56853E  
    56853 Technical Data, Rev. 6  
    6
    Freescale Semiconductor  
    Data Sheet Conventions  
    1.5 Data Sheet Conventions  
    This data sheet uses the following conventions:  
    OVERBAR  
    This is used to indicate a signal that is active when pulled low. For example, the RESET pin is  
    active when low.  
    “asserted”  
    “deasserted”  
    Examples:  
    A high true (active high) signal is high or a low true (active low) signal is low.  
    A high true (active high) signal is low or a low true (active low) signal is high.  
    Voltage1  
    Signal/Symbol  
    Logic State  
    True  
    Signal State  
    Asserted  
    PIN  
    PIN  
    PIN  
    PIN  
    VIL/VOL  
    False  
    Deasserted  
    Asserted  
    VIH/VOH  
    VIH/VOH  
    VIL/VOL  
    True  
    False  
    Deasserted  
    1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    7
    Part 2 Signal/Connection Descriptions  
    2.1 Introduction  
    The input and output signals of the 56853 are organized into functional groups, as shown in Table 2-1 and  
    as illustrated in Figure 2-1. In Table 3-1 each table row describes the package pin and the signal or signals  
    present.  
    Table 2-1 56853 Functional Group Pin Allocations  
    Functional Group  
    Number of Pins  
    (6, 11, 1)1  
    Power (VDD, VDDIO, or VDDA  
    )
    (6, 10, 1)1  
    Ground (VSS, VSSIO,or VSSA  
    )
    PLL and Clock  
    3
    39  
    4
    External Bus Signals  
    External Chip Select*  
    72  
    Interrupt and Program Control  
    Host Interface (HI)*  
    163  
    6
    Enhanced Synchronous Serial Interface (ESSI0) Port*  
    Serial Communications Interface (SCI0) Ports*  
    Serial Communications Interface (SCI1) Ports*  
    Serial Peripheral Interface (SPI) Port*  
    Quad Timer Module Port*  
    2
    2
    4
    4
    JTAG/Enhanced On-Chip Emulation (EOnCE)  
    *Alternately, GPIO pins  
    6
    1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA  
    2. MODA, MODB and MODC can be used as GPIO after the bootstrap process has completed.  
    3. The following Host Interface signals are multiplexed: HRWB to HRD, HDS to HWR, HREQ to HTRQ and HACK to HRRQ.  
    56853 Technical Data, Rev. 6  
    8
    Freescale Semiconductor  
    Introduction  
    RXDO (GPIOE0)  
    TXDO (GPIOE1)  
    VDD  
    VSS  
    1
    1
    SCI 0  
    SCI 2  
    Logic  
    Power  
    6
    6
    RXD1 (GPIOE2)  
    TXD1 (GPIOE3)  
    1
    1
    VDDIO  
    VSSIO  
    I/O  
    Power  
    11  
    10  
    STD0 (GPIOC0)  
    1
    SRD0 (GPIOC1)  
    SCK0 (GPIOC2)  
    Analog  
    Power1  
    VDDA  
    VSSA  
    1
    1
    1
    ESSI 0  
    1
    SC00 (GPIOC3)  
    SC01 (GPIOC4)  
    SC02 (GPIOC5)  
    1
    1
    56853  
    A0 - A20  
    D0 - D15  
    RD  
    1
    21  
    16  
    1
    External  
    Bus  
    WR  
    1
    Chip  
    Select  
    CS0 - CS3 (GPIOA0 - A3)  
    4
    HD0 - HD7 (GPIOB0 - B7)  
    HA0 - HA2 (GPIOB8 - B10)  
    HRWB (HRD) (GPIOB11)  
    HDS (HWR) (GPIOB12)  
    HCS (GPIOB13)  
    8
    3
    MISO (GPIOF0)  
    1
    1
    1
    MOSI (GPIOF1)  
    SCK (GPIOF2)  
    1
    1
    SPI  
    Host  
    Interface  
    SS (GPIOF3)  
    1
    1
    1
    HREQ (HTRQ) (GPIOB14)  
    HACK (HRRQ) (GPIOB15)  
    XTAL  
    1
    1
    1
    1
    EXTAL  
    CLKO  
    PLL /  
    Timer  
    TIO0 - TIO3 (GPIOG0 - G3)  
    4
    Clock  
    Module  
    TCK  
    IRQA  
    IRQB  
    1
    1
    1
    TDI  
    1
    1
    1
    1
    JTAG /  
    TDO  
    TMS  
    MODA, MODB, MODC  
    (GPIOH0 - H2)  
    Enhanced  
    OnCE  
    Interrupt /  
    Program  
    Control  
    3
    RESET  
    RSTO  
    TRST  
    DE  
    1
    1
    1
    2
    Figure 2-1 56853 Signals Identified by Functional Group  
    1. Specifically for PLL, OSC, and POR.  
    2. Alternate pin functions are shown in parentheses.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    9
    Part 3 Signals and Package Information  
    All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are  
    enabled by default. Exceptions:  
    1. When a pin has GPIO functionality, the pull-up may be disabled under software control.  
    2. MODE A, MODE B and MODE C pins have no pull-up.  
    3. TCK has a weak pull-down circuit always active.  
    4. Bidirectional I/O pullups automatically disable when the output is enabled.  
    This table is presented consistently with the Signals Identified by Functional Group figure.  
    1. BOLD entries in the Type column represents the state of the pin just out of reset.  
    2. Output(Z) means an output in a High-Z condition  
    Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP  
    Pin No.  
    13  
    Signal Name  
    VDD  
    Type  
    Description  
    VDD  
    Power (VDD)—These pins provide power to the internal structures of  
    the chip, and should all be attached to VDD.  
    47  
    VDD  
    64  
    VDD  
    79  
    VDD  
    80  
    VDD  
    112  
    14  
    VDD  
    VSS  
    VSS  
    Ground (VSS)—These pins provide grounding for the internal  
    structures of the chip and should all be attached to VSS.  
    48  
    VSS  
    63  
    VSS  
    81  
    VSS  
    96  
    VSS  
    113  
    VSS  
    56853 Technical Data, Rev. 6  
    10  
    Freescale Semiconductor  
    Introduction  
    Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)  
    Pin No.  
    5
    Signal Name  
    VDDIO  
    VDDIO  
    VDDIO  
    VDDIO  
    VDDIO  
    VDDIO  
    VDDIO  
    VDDIO  
    VDDIO  
    VDDIO  
    VDDIO  
    VSSIO  
    VSSIO  
    VSSIO  
    VSSIO  
    VSSIO  
    VSSIO  
    VSSIO  
    VSSIO  
    VSSIO  
    VSSIO  
    VDDA  
    Type  
    Description  
    VDDIO  
    Power (VDDIO)—These pins provide power for all I/O and ESD  
    structures of the chip, and should all be attached to VDDIO (3.3V).  
    18  
    41  
    55  
    61  
    72  
    91  
    92  
    100  
    114  
    124  
    6
    VSSIO  
    Ground (VSSIO)—These pins provide grounding for all I/O and ESD  
    structures of the chip and should all be attached to VSS.  
    19  
    42  
    56  
    62  
    74  
    93  
    102  
    115  
    125  
    22  
    VDDA  
    VSSA  
    Analog Power (VDDA)—These pins supply an analog power source.  
    Analog Ground (VSSA)—This pin supplies an analog ground.  
    23  
    VSSA  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    11  
    Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)  
    Pin No.  
    Signal Name  
    Type  
    Description  
    9
    A0  
    A1  
    Output(Z)  
    Address Bus (A0-A20)—These signals specify a word address for  
    external program or data memory access.  
    10  
    11  
    12  
    26  
    27  
    28  
    29  
    43  
    44  
    45  
    46  
    57  
    58  
    59  
    60  
    67  
    68  
    69  
    70  
    71  
    A2  
    A3  
    A4  
    A5  
    A6  
    A7  
    A8  
    A9  
    A10  
    A11  
    A12  
    A13  
    A14  
    A15  
    A16  
    A17  
    A18  
    A19  
    A20  
    56853 Technical Data, Rev. 6  
    12  
    Freescale Semiconductor  
    Introduction  
    Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)  
    Pin No.  
    Signal Name  
    Type  
    Description  
    73  
    86  
    D0  
    D1  
    Input/Output(Z) Data Bus (D0-D15)—These pins provide the bidirectional data for  
    external program or data memory accesses.  
    87  
    D2  
    88  
    D3  
    89  
    D4  
    90  
    D5  
    107  
    108  
    109  
    110  
    111  
    122  
    123  
    126  
    127  
    128  
    7
    D6  
    D7  
    D8  
    D9  
    D10  
    D11  
    D12  
    D13  
    D14  
    D15  
    RD  
    Output  
    Output  
    Read Enable (RD) —is asserted during external memory read cycles.  
    This signal is pulled high during reset.  
    8
    WR  
    Write Enable (WR)— is asserted during external memory write  
    cycles.  
    This signal is pulled high during reset.  
    75  
    76  
    77  
    78  
    Output  
    CS0  
    External Chip Select (CS0)—This pin is used as a dedicated GPIO.  
    Input/Output  
    GPIOA0  
    Port A GPIO (0) —This pin is a General Purpose I/O (GPIO) pin when  
    not configured for host port usage.  
    Output  
    CS1  
    External Chip Select (CS1)—This pin is used as a dedicated GPIO.  
    Input/Output  
    GPIOA1  
    Port A GPIO (1) —This pin is a General Purpose I/O (GPIO) pin when  
    not configured for host port usage.  
    Output  
    CS2  
    External Chip Select (CS2)—This pin is used as a dedicated GPIO.  
    Input/Output  
    GPIOA2  
    Port A GPIO (2) —This pin is a General Purpose I/O (GPIO) pin when  
    not configured for host port usage.  
    Output  
    CS3  
    External Chip Select (CS3)—This pin is used as a dedicated GPIO.  
    Input/Output  
    GPIOA3  
    Port A GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when  
    not configured for host port usage.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    13  
    Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)  
    Pin No.  
    Signal Name  
    Type  
    Input  
    Description  
    30  
    HD0  
    Host Address (HD0)—This input provides data selection for HI  
    registers.  
    This pin is disconnected internally during reset.  
    GPIOB0  
    HD1  
    Input/Output  
    Port B GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when  
    not configured for host port usage.  
    31  
    32  
    36  
    37  
    38  
    Input  
    Host Address (HD1)—This input provides data selection for HI  
    registers.  
    This pin is disconnected internally during reset.  
    GPIOB1  
    HD2  
    Input/Output  
    Port B GPIO (1)—This pin is a General Purpose I/O (GPIO) pin when  
    not configured for host port usage.  
    Input  
    Host Address (HD2)—This input provides data selection for HI  
    registers.  
    This pin is disconnected internally during reset.  
    GPIOB2  
    HD3  
    Input/Output  
    Port B GPIO (2)—This pin is a General Purpose I/O (GPIO) pin when  
    not configured for host port usage.  
    Input  
    Host Address (HD3)—This input provides data selection for HI  
    registers.  
    This pin is disconnected internally during reset.  
    GPIOB3  
    HD4  
    Input/Output  
    Port B GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when  
    not configured for host port usage.  
    Input  
    Host Address (HD4)—This input provides data selection for HI  
    registers.  
    This pin is disconnected internally during reset.  
    GPIOB4  
    HD5  
    Input/Output  
    Port B GPIO (4)—This pin is a General Purpose I/O (GPIO) pin when  
    not configured for host port usage.  
    Input  
    Host Address (HD5)—This input provides data selection for HI  
    registers.  
    This pin is disconnected internally during reset.  
    GPIOB5  
    Input/Output  
    Port B GPIO (5)—This pin is a General Purpose I/O (GPIO) pin when  
    not configured for host port usage.  
    56853 Technical Data, Rev. 6  
    14  
    Freescale Semiconductor  
    Introduction  
    Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)  
    Pin No.  
    Signal Name  
    Type  
    Input  
    Description  
    39  
    HD6  
    Host Address (HD6)—This input provides data selection for HI  
    registers.  
    This pin is disconnected internally during reset.  
    GPIOB6  
    HD7  
    Input/Output  
    Port B GPIO (6)—This pin is a General Purpose I/O (GPIO) pin when  
    not configured for host port usage.  
    40  
    82  
    83  
    84  
    85  
    Input  
    Host Address (HD7)—This input provides data selection for HI  
    registers.  
    This pin is disconnected internally during reset.  
    GPIOB7  
    HA0  
    Input/Output  
    Port B GPIO (7)—This pin is a General Purpose I/O (GPIO) pin when  
    not configured for host port usage.  
    Input  
    Host Address (HA0)—These inputs provide the address selection for  
    HI registers.  
    These pins are disconnected internally during reset.  
    GPIOB8  
    HA1  
    Input/Output  
    Port B GPIO (8)—These pins are General Purpose I/O (GPIO) pins  
    when not configured for host port usage.  
    Input  
    Host Address (HA0)—These inputs provide the address selection for  
    HI registers.  
    These pins are disconnected internally during reset.  
    GPIOB9  
    HA2  
    Input/Output  
    Port B GPIO (9)—These pins are General Purpose I/O (GPIO) pins  
    when not configured for host port usage.  
    Input  
    Host Address (HA0)—These inputs provide the address selection for  
    HI registers.  
    These pins are disconnected internally during reset.  
    GPIOB10  
    HRWB  
    Input/Output  
    Port B GPIO (10)—These pins are General Purpose I/O (GPIO) pins  
    when not configured for host port usage.  
    Input  
    Host Read/Write (HRWB)—When the HI08 is programmed to  
    interface to a single-data-strobe host bus and the HI function is  
    selected, this signal is the Read/Write input.  
    These pins are disconnected internally.  
    HRD  
    Input  
    Host Read Data (HRD)—This signal is the Read Data input when the  
    HI08 is programmed to interface to a double-data-strobe host bus and  
    the HI function is selected.  
    GPIOB11  
    Input/Output  
    Port B GPIO (11)—This pin is a General Purpose I/O (GPIO) pin  
    when not configured for host port usage.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    15  
    Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)  
    Pin No.  
    Signal Name  
    Type  
    Input  
    Description  
    103  
    HDS  
    Host Data Strobe (HDS)—When the HI08 is programmed to  
    interface to a single-data-strobe host bus and the HI function is  
    selected, this input enables a data transfer on the HI when HCS is  
    asserted.  
    These pins are disconnected internally.  
    HWR  
    Input  
    Host Write Enable (HWR)—This signal is the Write Data input when  
    the HI08 is programmed to interface to a double-data-strobe host bus  
    and the HI function is selected.  
    GPIOB12  
    HCS  
    Input/Output  
    Port B GPIO (12)—This pin is a General Purpose I/O (GPIO) pin  
    when not configured for host port usage.  
    104  
    105  
    Input  
    Host Chip Select (HCS)—This input is the chip select input for the  
    Host Interface.  
    These pins are disconnected internally.  
    GPIOB13  
    HREQ  
    Input/Output  
    Port B GPIO (13)—This pin is a General Purpose I/O (GPIO) pin  
    when not configured for host port usage.  
    Open Drain  
    Output  
    Host Request (HREQ)—When the HI08 is programmed for HRMS=0  
    functionality (typically used on a single-data-strobe bus), this open  
    drain output is used by the HI to request service from the host  
    processor. The HREQ may be connected to an interrupt request pin  
    of a host processor, a transfer request of a DMA controller, or a  
    control input of external circuitry.  
    These pins are disconnected internally.  
    HTRQ  
    Open Drain  
    Output  
    Transmit Host Request (HTRQ)—This signal is the Transmit Host  
    Request output when the HI08 is programmed for HRMS=1  
    functionality and is typically used on a double-data-strobe bus.  
    GPIOB14  
    Input/Output  
    Port B GPIO (14)—This pin is a General Purpose I/O (GPIO) pin  
    when not configured for host port usage.  
    56853 Technical Data, Rev. 6  
    16  
    Freescale Semiconductor  
    Introduction  
    Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)  
    Pin No.  
    Signal Name  
    Type  
    Input  
    Description  
    106  
    HACK  
    Host Acknowledge (HACK)—When the HI08 is programmed for  
    HRMS=0 functionality (typically used on a single-data-strobe bus),  
    this input has two functions: (1) provide a Host Acknowledge signal  
    for DMA transfers or (2) to control handshaking and provide a Host  
    Interrupt Acknowledge compatible with the MC68000 family  
    processors.  
    These pins are disconnected internally.  
    HRRQ  
    Open Drain  
    Output  
    Receive Host Request (HRRQ)—This signal is the Receive Host  
    Request output when the HI08 is programmed for HRMS=1  
    functionality and is typically used on a double-data-strobe bus.  
    GPIOB15  
    TIO0  
    Input/Output  
    Port B GPIO(15)—This pin is a General Purpose I/O (GPIO) pin  
    when not configured for host port usage.  
    101  
    99  
    Input/Output  
    Timer Input/Outputs (TIO0)—This pin can be independently  
    configured to be either a timer input source or an output flag.  
    GPIOG0  
    TIO1  
    Input/Output  
    Port G GPIOG0—This pin is a General Purpose I/O (GPIO) pin that  
    can individually be programmed as an input or output pin.  
    Input/Output  
    Timer Input/Outputs (TIO1)—This pin can be independently  
    configured to be either a timer input source or an output flag.  
    GPIOG1  
    TIO2  
    Input/Output  
    Port G GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that  
    can individually be programmed as an input or output pin.  
    98  
    Input/Output  
    Timer Input/Outputs (TIO2)—This pin can be independently  
    configured to be either a timer input source or an output flag.  
    GPIOG2  
    TIO3  
    Input/Output  
    Port G GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that  
    can individually be programmed as an input or output pin.  
    97  
    Input/Output  
    Timer Input/Outputs (TIO3)—This pin can be independently  
    configured to be either a timer input source or an output flag.  
    GPIOG3  
    Input/Output  
    Input  
    Port G GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that  
    can individually be programmed as an input or output pin.  
    20  
    21  
    IRQA  
    IRQB  
    External Interrupt Request A and B—The IRQA and IRQB inputs  
    are asynchronous external interrupt requests that indicate that an  
    external device is requesting service. A Schmitt trigger input is used  
    for noise immunity. They can be programmed to be level-sensitive or  
    negative-edge- triggered. If level-sensitive triggering is selected, an  
    external pull-up resistor is required for Wired-OR operation.  
    15  
    MODA  
    Input  
    Mode Select (MODA)—During the bootstrap process MODA selects  
    one of the eight bootstrap modes.  
    GPIOH0  
    Input/Output  
    Port H GPIO (0)—This pin is a General Purpose I/O (GPIO) pin after  
    the bootstrap process has completed.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    17  
    Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)  
    Pin No.  
    Signal Name  
    Type  
    Input  
    Description  
    16  
    MODB  
    Mode Select (MODB)—During the bootstrap process MODB selects  
    one of the eight bootstrap modes.  
    GPIOH1  
    MODC  
    Input/Output  
    Port H GPIO (1)—This pin is a General Purpose I/O (GPIO) pin after  
    the bootstrap process has completed.  
    17  
    35  
    Input  
    Mode Select (MODC)—During the bootstrap process MODC selects  
    one of the eight bootstrap modes.  
    GPIOH2  
    RESET  
    Input/Output  
    Input  
    Port H GPIO (2)—This pin is a General Purpose I/O (GPIO) pin after  
    the bootstrap process has completed.  
    Reset (RESET)—This input is a direct hardware reset on the  
    processor. When RESET is asserted low, the device is initialized and  
    placed in the Reset state. A Schmitt trigger input is used for noise  
    immunity. When the RESET pin is deasserted, the initial chip  
    operating mode is latched from the MODA, MODB, and MODC pins.  
    To ensure complete hardware reset, RESET and TRST should be  
    asserted together. The only exception occurs in a debugging  
    environment when a hardware reset is required and it is necessary  
    not to reset the JTAG/Enhanced OnCE module. In this case, assert  
    RESET, but do not assert TRST.  
    34  
    65  
    RSTO  
    RXD0  
    Output  
    Reset Output (RSTO)—This output is asserted on any reset  
    condition (external reset, low voltage, software or COP).  
    Input  
    Serial Receive Data 0 (RXD0)—This input receives byte-oriented  
    serial data and transfers it to the SCI 0 receive shift register.  
    GPIOE0  
    TXD0  
    Input/Output  
    Port E GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that  
    can individually be programmed as input or output pin.  
    66  
    94  
    95  
    Output(Z)  
    Serial Transmit Data 0 (TXD0)—This signal transmits data from the  
    SCI 0 transmit data register.  
    GPIOE1  
    RXD1  
    Input/Output  
    Port E GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that  
    can individually be programmed as input or output pin.  
    Input  
    Serial Receive Data 1 (RXD1)—This input receives byte-oriented  
    serial data and transfers it to the SCI 1 receive shift register.  
    GPIOE2  
    TXD1  
    Input/Output  
    Port E GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that  
    can individually be programmed as input or output pin.  
    Output(Z)  
    Serial Transmit Data 1 (TXD1)—This signal transmits data from the  
    SCI 1 transmit data register.  
    GPIOE3  
    Input/Output  
    Port E GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that  
    can individually be programmed as input or output pin.  
    56853 Technical Data, Rev. 6  
    18  
    Freescale Semiconductor  
    Introduction  
    Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)  
    Pin No.  
    Signal Name  
    Type  
    Description  
    116  
    STD0  
    Output  
    ESSI Transmit Data (STD0)—This output pin transmits serial data  
    from the ESSI Transmitter Shift Register.  
    GPIOC0  
    SRD0  
    Input/Output  
    Port C GPIO (0)—This pin is a General Purpose I/O (GPIO) pin when  
    the ESSI is not in use.  
    117  
    118  
    Input  
    ESSI Receive Data (SRD0)—This input pin receives serial data and  
    transfers the data to the ESSI Receive Shift Register.  
    GPIOC1  
    SCK0  
    Input/Output  
    Input/Output  
    Port C GPIO (1)—This pin is a General Purpose I/O (GPIO) pin when  
    the ESSI is not in use.  
    ESSI Serial Clock (SCK0)—This bidirectional pin provides the serial  
    bit rate clock for the transmit section of the ESSI. The clock signal can  
    be continuous or gated and can be used by both the transmitter and  
    receiver in synchronous mode.  
    GPIOC2  
    SC00  
    Input/Output  
    Port C GPIO (2)—This pin is a General Purpose I/O (GPIO) pin when  
    the ESSI is not in use.  
    119  
    120  
    121  
    Input/Output  
    ESSI Serial Control Pin 0 (SC00)—The function of this pin is  
    determined by the selection of either synchronous or asynchronous  
    mode. For asynchronous mode, this pin will be used for the receive  
    clock I/O. For synchronous mode, this pin is used either for  
    transmitter1 output or for serial I/O flag 0.  
    GPIOC3  
    SC01  
    Input/Output  
    Port C GPIO (3)—This pin is a General Purpose I/O (GPIO) pin when  
    the ESSI is not in use.  
    Input/Output  
    ESSI Serial Control Pin 1 (SC01)—The function of this pin is  
    determined by the selection of either synchronous or asynchronous  
    mode. For asynchronous mode, this pin is the receiver frame sync  
    I/O. For synchronous mode, this pin is used either for transmitter2  
    output or for serial I/O flag 1.  
    GPIOC4  
    SC02  
    Input/Output  
    Port C GPIO (4)—This pin is a General Purpose I/O (GPIO) pin when  
    the ESSI is not in use.  
    Input/Output  
    ESSI Serial Control Pin 2 (SC02)—This pin is used for frame sync  
    I/O. SC02 is the frame sync for both the transmitter and receiver in  
    synchronous mode and for the transmitter only in asynchronous  
    mode. When configured as an output, this pin is the internally  
    generated frame sync signal. When configured as an input, this pin  
    receives an external frame sync signal for the transmitter (and the  
    receiver in synchronous operation).  
    GPIOC5  
    Input /Output  
    Port C GPIO (5)—This pin is a General Purpose I/O (GPIO) pin when  
    the ESSI is not in use.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    19  
    Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)  
    Pin No.  
    Signal Name  
    Type  
    Description  
    1
    MISO  
    Input/Output  
    SPI Master In/Slave Out (MISO)—This serial data pin is an input to a  
    master device and an output from a slave device. The MISO line of a  
    slave device is placed in the high-impedance state if the slave device  
    is not selected. The driver on this pin can be configured as an  
    open-drain driver by the SPI’s Wired-OR mode (WOM) bit when this  
    pin is configured for SPI operation.  
    GPIOF0  
    MOSI  
    Input/Output  
    Port F GPIO (0)—This pin is a General Purpose I/O (GPIO) pin that  
    can be individually programmed as input or output pin.  
    2
    Input/Output (Z) SPI Master Out/Slave In (MOSI)—This serial data pin is an output  
    from a master device and an input to a slave device. The master  
    device places data on the MOSI line a half-cycle before the clock  
    edge that the slave device uses to latch the data. The driver on this  
    pin can be configured as an open-drain driver by the SPI’s WOM bit  
    when this pin is configured for SPI operation.  
    GPIOF1  
    SCK  
    Input/Output  
    Port F GPIO (1)—This pin is a General Purpose I/O (GPIO) pin that  
    can individually be programmed as input or output pin.  
    3
    Input/Output  
    SPI Serial Clock (SCK)—This bidirectional pin provides a serial bit  
    rate clock for the SPI. This gated clock signal is an input to a slave  
    device and is generated as an output by a master device. Slave  
    devices ignore the SCK signal unless the SS pin is active low. In both  
    master and slave SPI devices, data is shifted on one edge of the SCK  
    signal and is sampled on the opposite edge, where data is stable. The  
    driver on this pin can be configured as an open-drain driver by the  
    SPI’s WOM bit when this pin is configured for SPI operation. When  
    using Wired-OR mode, the user must provide an external pull-up  
    device.  
    GPIOF2  
    SS  
    Input/Output  
    Port F GPIO (2)—This pin is a General Purpose I/O (GPIO) pin that  
    can be individually programmed as input or output pin.  
    4
    Input  
    SPI Slave Select (SS)—This input pin selects a slave device before a  
    master device can exchange data with the slave device. SS must be  
    low before data transactions and must stay low for the duration of the  
    transaction. The SS line of the master must be held high.  
    GPIOF3  
    XTAL  
    Input/Output  
    Port F GPIO (3)—This pin is a General Purpose I/O (GPIO) pin that  
    can individually be programmed as input or output pin.  
    24  
    25  
    33  
    Input/Output  
    Crystal Oscillator Output (XTAL)—This output connects the internal  
    crystal oscillator output to an external crystal. If an external clock  
    source other than a crystal oscillator is used, XTAL must be used as  
    the input.  
    EXTAL  
    CLKO  
    Input  
    External Crystal Oscillator Input (EXTAL)—This input should be  
    connected to an external crystal. If an external clock source other  
    than a crystal oscillator is used, EXTAL must be tied off. See Section  
    4.5.2  
    Output  
    Clock Output (CLKO)—This pin outputs a buffered clock signal.  
    When enabled, this signal is the system clock divided by four.  
    56853 Technical Data, Rev. 6  
    20  
    Freescale Semiconductor  
    Introduction  
    Table 3-1. 56853 Signal and Package Information for the 128-pin LQFP (Continued)  
    Pin No.  
    Signal Name  
    Type  
    Description  
    54  
    TCK  
    Input  
    Test Clock Input (TCK)—This input pin provides a gated clock to  
    synchronize the test logic and to shift serial data to the  
    JTAG/Enhanced OnCE port. The pin is connected internally to a  
    pull-down resistor.  
    52  
    51  
    TDI  
    Input  
    Test Data Input (TDI)—This input pin provides a serial input data  
    stream to the JTAG/Enhanced OnCE port. It is sampled on the rising  
    edge of TCK and has an on-chip pull-up resistor.  
    TDO  
    Output (Z)  
    Test Data Output (TDO)—This tri-statable output pin provides a  
    serial output data stream from the JTAG/Enhanced OnCE port. It is  
    driven in the Shift-IR and Shift-DR controller states, and changes on  
    the falling edge of TCK.  
    53  
    50  
    TMS  
    Input  
    Input  
    Test Mode Select Input (TMS)—This input pin is used to sequence  
    the JTAG TAP controller’s state machine. It is sampled on the rising  
    edge of TCK and has an on-chip pull-up resistor.  
    Note: Always tie the TMS pin to VDD through a 2.2K resistor.  
    TRST  
    Test Reset (TRST)—As an input, a low signal on this pin provides a  
    reset signal to the JTAG TAP controller. To ensure complete  
    hardware reset, TRST should be asserted whenever RESET is  
    asserted. The only exception occurs in a debugging environment,  
    since the Enhanced OnCE/JTAG module is under the control of the  
    debugger. In this case it is not necessary to assert TRST when  
    asserting RESET. Outside of a debugging environment RESET  
    should be permanently asserted by grounding the signal, thus  
    disabling the Enhanced OnCE/JTAG module on the controller.  
    Note: For normal operation, connect TRST directly to VSS. If the design  
    is to be used in a debugging environment, TRST may be tied to VSS through  
    a 1K resistor.  
    49  
    DE  
    Input/Output  
    Debug Event (DE)—This is an open-drain, bidirectional, active low  
    signal. As an input, it is a means of entering debug mode of operation  
    from an external command controller. As an output, it is a means of  
    acknowledging that the chip has entered debug mode.  
    This pin is connected internally to a weak pull-up resistor.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    21  
    Part 4 Specifications  
    4.1 General Characteristics  
    The 56853 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The  
    term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process  
    technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a  
    mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V  
    and 5V- compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of  
    3.3V ± 10% during normal operation without causing damage). This 5V tolerant capability therefore  
    offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.  
    Absolute maximum ratings given in Table 4-1 are stress ratings only, and functional operation at the  
    maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent  
    damage to the device.  
    The 56853 DC/AC electrical specifications are preliminary and are from design simulations. These  
    specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized  
    specifications will be published after complete characterization and device qualifications have been  
    completed.  
    CAUTION  
    This device contains protective circuitry to guard  
    against damage due to high static voltage or  
    electrical fields. However, normal precautions are  
    advised to avoid application of any voltages higher  
    than maximum rated voltages to this high-impedance  
    circuit. Reliability of operation is enhanced if unused  
    inputs are tied to an appropriate voltage level.  
    56853 Technical Data, Rev. 6  
    22  
    Freescale Semiconductor  
    General Characteristics  
    Table 4-1 Absolute Maximum Ratings  
    Characteristic  
    Supply voltage, core  
    Symbol  
    Min  
    Max  
    Unit  
    1
    VSS – 0.3  
    VSS + 2.0  
    V
    VDD  
    2
    V
    VDDIO  
    VSSIO – 0.3  
    VSSA – 0.3  
    VSSIO + 4.0  
    VDDA + 4.0  
    Supply voltage, IO  
    Supply voltage, analog  
    2
    VDDIO  
    Digital input voltages  
    Analog input voltages (XTAL, EXTAL)  
    VIN  
    VSSIO – 0.3  
    VSSA – 0.3  
    VSSIO + 5.5  
    VDDA + 0.3  
    V
    VINA  
    Current drain per pin excluding VDD, GND  
    Junction temperature  
    I
    —
    8
    mA  
    °C  
    TJ  
    -40  
    -55  
    120  
    150  
    Storage temperature range  
    TSTG  
    °C  
    1. VDD must not exceed VDDIO  
    2. VDDIO and VDDA must not differ by more that 0.5V  
    Table 4-2 Recommended Operating Conditions  
    Characteristic  
    Supply voltage for Logic Power  
    Symbol  
    VDD  
    VDDIO  
    VDDA  
    TA  
    Min  
    1.62  
    3.0  
    3.0  
    -40  
    —
    Max  
    1.98  
    3.6  
    3.6  
    85  
    Unit  
    V
    Supply voltage for I/O Power  
    Supply voltage for Analog Power  
    Ambient operating temperature  
    V
    V
    °C  
    PLL clock frequency1  
    fpll  
    240  
    120  
    60  
    MHz  
    MHz  
    MHz  
    MHz  
    MHz  
    MHz  
    MHz  
    Operating Frequency2  
    fop  
    —
    Frequency of peripheral bus  
    fipb  
    —
    Frequency of external clock  
    Frequency of oscillator  
    fclk  
    —
    240  
    4
    fosc  
    2
    Frequency of clock via XTAL  
    Frequency of clock via EXTAL  
    fxtal  
    —
    240  
    4
    fextal  
    2
    1.Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz. PLL must be enabled, locked, and  
    selected. The actual frequency depends on the source clock frequency and programming of the CGM module.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    23  
    2.Master clock is derived from on of the following four sources:  
    fclk = fxtal when the source clock is the direct clock to EXTAL  
    fclk = fpll when PLL is selected  
    fclk = fosc when the source clock is the crystal oscillator and PLL is not selected  
    fclk = fextal when the source clock is the direct clock to EXTAL and PLL is not selected  
    1
    Table 4-3 Thermal Characteristics  
    128-pin LQFP  
    Value  
    Characteristic  
    Symbol  
    Unit  
    Thermal resistance junction-to-ambient  
    (estimated)  
    θJA  
    43.1  
    °C/W  
    I/O pin power dissipation  
    Power dissipation  
    PI/O  
    PD  
    User Determined  
    W
    W
    W
    PD = (IDD × VDD) + PI/O  
    2
    Maximum allowed PD  
    PDMAX  
    (TJ – TA) / RθJA  
    1. See Section 6.1 for more detail.  
    2. TJ = Junction Temperature  
    TA = Ambient Temperature  
    4.2 DC Electrical Characteristics  
    Table 4-4 DC Electrical Characteristics  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    = V  
    = 3.0–3.6V, T = –40  
    °
    to +120  
    °
    C, C ≤  
    50pF, f = 120MHz  
    op  
    SS  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA  
    A
    L
    Characteristic  
    Input high voltage (XTAL/EXTAL)  
    Input low voltage (XTAL/EXTAL)  
    Input high voltage  
    Symbol  
    VIHC  
    VILC  
    VIH  
    Min  
    Typ  
    VDDA  
    —
    Max  
    Unit  
    V
    VDDA – 0.8  
    VDDA + 0.3  
    -0.3  
    0.5  
    5.5  
    0.8  
    1
    V
    2.0  
    —
    V
    Input low voltage  
    VIL  
    -0.3  
    —
    V
    Input current low (pullups disabled)  
    Input current high (pullups disabled)  
    Output tri-state current low  
    Output tri-state current high  
    Output High Voltage  
    IIL  
    -1  
    —
    μA  
    μA  
    μA  
    μA  
    V
    IIH  
    -1  
    —
    1
    IOZL  
    IOZH  
    VOH  
    VOL  
    IOH  
    -10  
    —
    10  
    10  
    —
    0.4  
    16  
    -10  
    —
    VDDIO – 0.7  
    —
    Output Low Voltage  
    —
    8
    —
    V
    Output High Current  
    —
    mA  
    56853 Technical Data, Rev. 6  
    24  
    Freescale Semiconductor  
    DC Electrical Characteristics  
    Table 4-4 DC Electrical Characteristics (Continued)  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    = V  
    = 3.0–3.6V, T = –40° to +120°C, C ≤ 50pF, f = 120MHz  
    SS  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA A L op  
    Characteristic  
    Symbol  
    IOL  
    Min  
    8
    Typ  
    —
    Max  
    16  
    Unit  
    mA  
    pF  
    Output Low Current  
    Input capacitance  
    Output capacitance  
    CIN  
    —
    8
    —
    COUT  
    —
    12  
    —
    pF  
    4
    VDD supply current (Core logic, memories, peripherals)  
    IDD  
    Run 1  
    —
    —
    —
    70  
    0.05  
    5
    110  
    10  
    14  
    mA  
    mA  
    mA  
    Deep Stop2  
    Light Stop3  
    VDDIO supply current (I/O circuity)  
    IDDIO  
    Run5  
    Deep Stop2  
    —
    40  
    0
    50  
    1.5  
    mA  
    mA  
    VDDA supply current (analog circuity)  
    Deep Stop2  
    IDDA  
    —
    —
    —
    —
    60  
    2.5  
    50  
    120  
    2.85  
    —
    μA  
    V
    Low Voltage Interrupt6  
    VEI  
    Low Voltage Interrupt Recovery Hysteresis  
    VEIH  
    POR  
    mV  
    V
    Power on Reset7  
    1.5  
    2.0  
    Note:  
    Run (operating) IDD measured using external square wave clock source (fosc = 4MHz) into XTAL. All inputs 0.2V from rail; no  
    DC loads; outputs unloaded. All ports configured as inputs; measured with all modules enabled. PLL set to 240MHz out.  
    1. Running Core, performing 50% NOP and 50% FIR. Clock at 120 MHz.  
    2. Deep Stop Mode - Operation frequency = 4 MHz, PLL set to 4 MHz, crystal oscillator and time of day module operating.  
    3. Light Stop Mode - Operation frequency = 120 MHz, PLL set to 240 MHz, crystal oscillator and time of day module operating.  
    4. IDD includes current for core logic, internal memories, and all internal peripheral logic circuitry.  
    5. Running core and performing external memory access. Clock at 120 MHz.  
    6. When VDD drops below VEI max value, an interrupt is generated.  
    7. Power-on reset occurs whenever the digital supply drops below 1.8V. While power is ramping up, this signal remains active  
    for as long as the internal 2.5V is below 1.8V no matter how long the ramp up rate is. The internally regulated voltage is  
    typically 100 mV less than VDD during ramp up until 2.5V is reached, at which time it self-regulates.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    25  
    150  
    MAC Mode1  
    EMI Mode5  
    120  
    90  
    60  
    30  
    0
    20  
    40  
    120  
    100  
    60  
    80  
    Figure 4-1 Maximum Run I  
    vs. Frequency (see Notes 1. and 5. in Table 4-4)  
    DDTOTAL  
    56853 Technical Data, Rev. 6  
    26  
    Freescale Semiconductor  
    Supply Voltage Sequencing and Separation Cautions  
    4.3 Supply Voltage Sequencing and Separation Cautions  
    Figure 4-2 shows two situations to avoid in sequencing the V and V  
    V
    supplies.  
    DD  
    DDIO, DDA  
    3.3V  
    VDDIO, VDDA  
    2
    Supplies Stable  
    1.8V  
    VDD  
    1
    0
    Time  
    Notes: 1. VDD rising before VDDIO, VDDA  
    2. VDDIO, VDDA rising much faster than VDD  
    Figure 4-2 Supply Voltage Sequencing and Separation Cautions  
    V
    should not be allowed to rise early (1). This is usually avoided by running the regulator for the V  
    DD  
    DD  
    supply (1.8V) from the voltage generated by the 3.3V V  
    supply, see Figure 4-3. This keeps V from  
    DDIO  
    DD  
    rising faster than V  
    .
    DDIO  
    V
    should not rise so late that a large voltage difference is allowed between the two supplies (2).  
    DD  
    Typically this situation is avoided by using external discrete diodes in series between supplies, as shown  
    in Figure 4-3. The series diodes forward bias when the difference between V and V reaches  
    DDIO  
    DD  
    approximately 2.1, causing V to rise as V  
    ramps up. When the V regulator begins proper  
    DD  
    DDIO  
    DD  
    operation, the difference between supplies will typically be 0.8V and conduction through the diode chain  
    reduces to essentially leakage current. During supply sequencing, the following general relationship  
    should be adhered to:  
    V
    > V > (V  
    - 2.1V)  
    DDIO  
    DD  
    DDIO  
    In practice, V  
    is typically connected directly to V  
    with some filtering.  
    DDA  
    DDIO  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    27  
    VDDIO, VDDA  
    3.3V  
    Regulator  
    Supply  
    VDD  
    1.8V  
    Regulator  
    Figure 4-3 Example Circuit to Control Supply Sequencing  
    4.4 AC Electrical Characteristics  
    Timing waveforms in Section 4.2 are tested with a VIL maximum of 0.8 V and a VIH minimum of 2.0 V  
    for all pins except XTAL, which is tested using the input levels in Section 4.2. In Figure 4-4 the levels of  
    VIH and VIL for an input signal are shown.  
    Low  
    VIL  
    High  
    VIH  
    90%  
    50%  
    10%  
    Input Signal  
    Midpoint1  
    Fall Time  
    Note: The midpoint is VIL + (VIH – VIL)/2.  
    Rise Time  
    Figure 4-4 Input Signal Measurement References  
    Figure 4-5 shows the definitions of the following signal states:  
    •
    •
    •
    Active state, when a bus or signal is driven, and enters a low impedance state.  
    Tri-stated, when a bus or signal is placed in a high impedance state.  
    Data Valid state, when a signal level has reached VOL or VOH.  
    •
    Data Invalid state, when a signal level is in transition between VOL and VOH.  
    Data2 Valid  
    Data2  
    Data1 Valid  
    Data1  
    Data3 Valid  
    Data3  
    Data  
    Tri-stated  
    Data Invalid State  
    Data Active  
    Data Active  
    Figure 4-5 Signal States  
    56853 Technical Data, Rev. 6  
    28  
    Freescale Semiconductor  
    External Clock Operation  
    4.5 External Clock Operation  
    The 56853 system clock can be derived from a crystal or an external system clock signal. To generate a  
    reference frequency using the internal oscillator, a reference crystal must be connected between the  
    EXTAL and XTAL pins.  
    4.5.1  
    Crystal Oscillator  
    The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency  
    range specified for the external crystal in Table 4-6. In Figure 4-6 a typical crystal oscillator circuit is  
    shown. Follow the crystal supplier’s recommendations when selecting a crystal, because crystal  
    parameters determine the component values required to provide maximum stability and reliable start-up.  
    The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL  
    pins to minimize output distortion and start-up stabilization time.  
    Crystal Frequency = 2–4 MHz (optimized for 4MHz)  
    Sample External Crystal Parameters:  
    EXTAL XTAL  
    Rz = 10MΩ  
    TOD_SEL bit in CGM must be set to 0  
    Rz  
    Figure 4-6 Crystal Oscillator  
    4.5.2  
    High Speed External Clock Source (> 4MHz)  
    The recommended method of connecting an external clock is given in Figure 4-7. The external clock  
    source is connected to XTAL and the EXTAL pin is held at ground, V  
    bit in CGM must be set to 0.  
    , or V  
    /2. The TOD_SEL  
    DDA  
    DDA  
    DSP56853  
    XTAL  
    EXTAL  
    GND,VDDA  
    or VDDA/2  
    ,
    External  
    Clock  
    (up to 240MHz)  
    Figure 4-7 Connecting a High Speed External Clock Signal using XTAL  
    4.5.3  
    Low Speed External Clock Source (2-4MHz)  
    The recommended method of connecting an external clock is given in Figure 4-8. The external clock  
    source is connected to XTAL and the EXTAL pin is held at V  
    set to 0.  
    /2. The TOD_SEL bit in CGM must be  
    DDA  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    29  
    DSP56853  
    XTAL  
    EXTAL  
    External  
    Clock  
    VDDA/2  
    (2-4MHz)  
    Figure 4-8 Connecting a Low Speed External Clock Signal using XTAL  
    4
    Table 4-5 External Clock Operation Timing Requirements  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    = V  
    = 3.0–3.6V, T = –40° to +120°C, C ≤ 50pF, f = 120MHz  
    SS  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA A L op  
    Characteristic  
    Symbol  
    fosc  
    Min  
    0
    Typ  
    Max  
    240  
    —
    Unit  
    MHz  
    ns  
    Frequency of operation (external clock driver)1  
    Clock Pulse Width4  
    —
    —
    —
    —
    tPW  
    6.25  
    —
    External clock input rise time2, 4  
    External clock input fall time3, 4  
    trise  
    TBD  
    TBD  
    ns  
    tfall  
    —
    ns  
    1. See Figure 4-7 for details on using the recommended connection of an external clock driver.  
    2. External clock input rise time is measured from 10% to 90%.  
    3. External clock input fall time is measured from 90% to 10%.  
    4. Parameters listed are guaranteed by design.  
    VIH  
    External  
    Clock  
    90%  
    50%  
    10%  
    90%  
    50%  
    10%  
    tPW  
    tPW  
    VIL  
    trise  
    tfall  
    Note: The midpoint is VIL + (VIH – VIL)/2.  
    Figure 4-9 External Clock Timing  
    56853 Technical Data, Rev. 6  
    30  
    Freescale Semiconductor  
    External Memory Interface Timing  
    Table 4-6 PLL Timing  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    = V  
    = 3.0–3.6V, T = –40° to +120°C, C ≤ 50pF, f = 120MHz  
    SS  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA A L op  
    Characteristic  
    Symbol  
    fosc  
    Min  
    2
    Typ  
    4
    Max  
    4
    Unit  
    MHz  
    MHz  
    ms  
    External reference crystal frequency for the PLL1  
    PLL output frequency  
    fclk  
    40  
    —
    —
    1
    240  
    10  
    PLL stabilization time 2  
    tplls  
    1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.  
    The PLL is optimized for 4MHz input crystal.  
    2. This is the minimum time required after the PLL setup is changed to ensure reliable operation.  
    4.6 External Memory Interface Timing  
    The External Memory Interface is designed to access static memory and peripheral devices. Figure 4-10 shows  
    sample timing and parameters that are detailed in Table 4-7.  
    The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as user  
    controlled wait states. The equation:  
    t = D + P * (M + W)  
    should be used to determine the actual time of each parameter. The terms in the above equation are defined as:  
    t
    parameter delay time  
    D fixed portion of the delay, due to on-chip path delays.  
    P
    the period of the system clock, which determines the execution rate of the part (i.e. when the device is  
    operating at 120 MHz, P = 8.33 ns).  
    M Fixed portion of a clock period inherent in the design. This number is adjusted to account for possible  
    clock duty cycle derating.  
    W the sum of the applicable wait state controls. See the “Wait State Controls” column of Table 4-7 for  
    the applicable controls for each parameter. See the EMI chapter of the 83x Peripheral Manual for  
    details of what each wait state field controls.  
    Some of the parameters contain two sets of numbers. These parameters have two different paths and clock edges  
    that must be considered. Check both sets of numbers and use the smaller result. The appropriate entry may change  
    if the operating frequency of the part changes.  
    The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters contain  
    two sets of numbers to account for this difference. The “Wait States Configuration” column of Table 4-7 should be  
    used to make the appropriate selection.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    31  
    A0-Axx,CS  
    tRD  
    tARDD  
    tRDA  
    tRDRD  
    tARDA  
    RD  
    tWAC  
    tWRRD  
    tAWR  
    tWRWR  
    tWR  
    tRDWR  
    WR  
    tDWR  
    tDOH  
    tRDD  
    tDOS  
    Data Out  
    tAD  
    tDRD  
    Data In  
    D0-D15  
    Note: During read-modify-write instructions and internal instructions, the address lines do not change state.  
    Figure 4-10 External Memory Interface Timing  
    Table 4-7 External Memory Interface Timing  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98 V, V  
    = V  
    = 3.0–3.6V, T = –40× to +120×C, C £ 50pF, P = 8.333ns  
    SS  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA  
    A
    L
    Wait States  
    Configuration  
    Wait States  
    Controls  
    Characteristic  
    Symbol  
    tAWR  
    D
    M
    Unit  
    ns  
    WWS=0  
    WWS>0  
    WWS=0  
    WWS>0  
    WWS=0  
    WWS=0  
    WWS>0  
    WWS>0  
    -0.79  
    -1.98  
    -0.86  
    -0.01  
    -1.52  
    - 5.69  
    -2.10  
    -4.66  
    0.50  
    0.69  
    0.19  
    0.00  
    0.00  
    0.25  
    0.19  
    0.50  
    Address Valid to WR Asserted  
    WWSS  
    WWS  
    WR Width Asserted to WR  
    Deasserted  
    tWR  
    ns  
    Data Out Valid to WR Asserted  
    tDWR  
    WWSS  
    ns  
    Valid Data Out Hold Time after WR  
    Deasserted  
    tDOH  
    -1.47  
    0.25  
    WWSH  
    WWS,WWSS  
    WWSH  
    ns  
    ns  
    -2.36  
    -4.67  
    0.19  
    0.50  
    Valid Data Out Set Up Time to WR  
    Deasserted  
    tDOS  
    tWAC  
    Valid Address after WR  
    Deasserted  
    -1.60  
    0.25  
    56853 Technical Data, Rev. 6  
    32  
    Freescale Semiconductor  
    Reset, Stop, Wait, Mode Select, and Interrupt Timing  
    Table 4-7 External Memory Interface Timing (Continued)  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98 V, V  
    = V  
    = 3.0–3.6V, T = –40× to +120×C, C £ 50pF, P = 8.333ns  
    SS  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA  
    A
    L
    Wait States  
    Configuration  
    Wait States  
    Controls  
    Characteristic  
    Symbol  
    D
    M
    Unit  
    tRDA  
    - 0.44  
    -2.07  
    0.00  
    1.00  
    RWSH  
    ns  
    ns  
    RD Deasserted to Address Invalid  
    Address Valid to RD Deasserted  
    tARDD  
    RWSS,RWS  
    Valid Input Data Hold after RD  
    Deasserted  
    N/A1  
    1.00  
    tDRD  
    tRD  
    0.00  
    —
    ns  
    ns  
    ns  
    ns  
    ns  
    -1.34  
    RWS  
    RD Assertion Width  
    -10.27  
    -13.5  
    1.00  
    1.19  
    Address Valid to Input Data Valid  
    tAD  
    RWSS,RWS  
    RWSS  
    tARDA  
    tRDD  
    tWRRD  
    tRDRD  
    tWRWR  
    - 0.94  
    0.00  
    Address Valid to RD Asserted  
    -9.53  
    1.00  
    1.19  
    RD Asserted to Input Data Valid  
    RWSS,RWS  
    WWSH,RWSS  
    RWSS,RWSH  
    -12.64  
    -0.75  
    0.25  
    0.00  
    ns  
    ns  
    WR Deasserted to RD Asserted  
    RD Deasserted to RD Asserted  
    WR Deasserted to WR Asserted  
    -0.162  
    -0.44  
    -0.11  
    0.14  
    WWS=0  
    WWS>0  
    0.75  
    1.00  
    0.50  
    0.69  
    WWSS, WWSH  
    ns  
    ns  
    MDAR, BMDAR,  
    RWSH, WWSS  
    RD Deasserted to WR Asserted  
    tRDWR  
    -0.57  
    1. N/A since device captures data before it deasserts RD  
    2. If RWSS = RWSH = 0, RD does not deassert during back-to-back reads and D=0.00 should be used.  
    4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing  
    1, 2  
    Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    = V  
    = 3.0–3.6V, T = –40  
    °
    to +120  
    °
    C, C ≤  
    50pF, f = 120MHz  
    op  
    SS  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA  
    A
    L
    Characteristic  
    Symbol  
    Min  
    Max  
    Unit  
    See Figure  
    4-11  
    RESET Assertion to Address, Data and Control  
    Signals High Impedance  
    tRAZ  
    —
    11  
    ns  
    Minimum RESET Assertion Duration3  
    tRA  
    tRDA  
    tIRW  
    30  
    —
    —
    120T  
    —
    ns  
    ns  
    ns  
    4-11  
    4-11  
    4-12  
    RESET Deassertion to First External Address Output  
    Edge-sensitive Interrupt Request Width  
    1T + 3  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    33  
    1, 2 (Continued)  
    Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    = V  
    = 3.0–3.6V, T = –40  
    °
    to +120  
    °
    C, C ≤  
    50pF, f = 120MHz  
    op  
    SS  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA  
    A
    L
    Characteristic  
    Symbol  
    tIDM  
    Min  
    18T  
    14T  
    18T  
    14T  
    22T  
    18T  
    Max  
    Unit  
    See Figure  
    4-13  
    IRQA, IRQB Assertion to External Data Memory  
    Access Out Valid, caused by first instruction execution  
    in the interrupt service routine  
    —
    —
    —
    —
    —
    —
    ns  
    tIDM -FAST  
    tIG  
    tIG -FAST  
    tIRI  
    tIRI -FAST  
    tIW  
    IRQA, IRQB Assertion to General Purpose Output  
    Valid, caused by first instruction execution in the  
    interrupt service routine  
    ns  
    ns  
    4-13  
    4-14  
    IRQA Low to First Valid Interrupt Vector Address Out  
    recovery from Wait State4  
    Delay from IRQA Assertion (exiting Stop) to External  
    Data Memory5  
    4-15  
    4-15  
    1.5T  
    —
    ns  
    Delay from IRQA Assertion (exiting Wait) to External  
    Data Memory  
    tIF  
    Fast6  
    Normal7  
    18T  
    22ET  
    ns  
    ns  
    —
    —
    RSTO pulse width8  
    normal operation  
    internal reset mode  
    tRSTO  
    4-16  
    128ET  
    8ET  
    —
    —
    —
    —
    1. In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.  
    2. Parameters listed are guaranteed by design.  
    3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source  
    clock, txtal, textal or tosc  
    .
    4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is  
    not the minimum required so that the IRQA interrupt is accepted.  
    5. The interrupt instruction fetch is visible on the pins only in Mode 3.  
    6. Fast stop mode:  
    Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is  
    requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes  
    one less cycle and tclk will continue same value it had before stop mode was entered.  
    7. Normal stop mode:  
    As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master  
    clock, recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate.  
    8. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.  
    56853 Technical Data, Rev. 6  
    34  
    Freescale Semiconductor  
    Reset, Stop, Wait, Mode Select, and Interrupt Timing  
    RESET  
    tRA  
    tRAZ  
    tRDA  
    A0–A20,  
    D0–D15  
    First Fetch  
    CS,  
    RD, WR  
    First Fetch  
    Figure 4-11 Asynchronous Reset Timing  
    IRQA  
    IRQB  
    tIRW  
    Figure 4-12 External Interrupt Timing (Negative-Edge-Sensitive)  
    A0–A20,  
    CS,  
    RD, WR  
    First Interrupt Instruction Execution  
    tIDM  
    IRQA,  
    IRQB  
    a) First Interrupt Instruction Execution  
    General  
    Purpose  
    I/O Pin  
    tIG  
    IRQA,  
    IRQB  
    b) General Purpose I/O  
    Figure 4-13 External Level-Sensitive Interrupt Timing  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    35  
    IRQA,  
    IRQB  
    tIRI  
    A0–A20,  
    CS,  
    RD, WR  
    First Interrupt Vector  
    Instruction Fetch  
    Figure 4-14 Interrupt from Wait State Timing  
    tIW  
    IRQA  
    tIF  
    A0–A20,  
    CS,  
    RD, WR  
    First Instruction Fetch  
    Not IRQA Interrupt Vector  
    Figure 4-15 Recovery from Stop State Using Asynchronous Interrupt Timing  
    RESET  
    tRSTO  
    Figure 4-16 Reset Output Timing  
    4.8 Host Interface Port  
    1
    Table 4-9 Host Interface Port Timing  
    Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz  
    Characteristic  
    Symbol  
    Min  
    Max  
    Unit  
    See Figure  
    TACKDV  
    TACKDZ  
    Access time  
    Disable time  
    —
    3
    13  
    —
    ns  
    ns  
    4-17  
    4-17  
    4-17,  
    4-20  
    TACKREQH  
    TREQACKL  
    Time to disassert  
    Lead time  
    3.5  
    0
    9
    ns  
    ns  
    4-17  
    4-20  
    —
    56853 Technical Data, Rev. 6  
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    Host Interface Port  
    1
    Table 4-9 Host Interface Port Timing  
    Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz  
    Characteristic  
    Symbol  
    Min  
    Max  
    Unit  
    See Figure  
    ns  
    4-18  
    4-19  
    TRADV  
    Access time  
    —
    13  
    ns  
    ns  
    4-18  
    4-19  
    TRADX  
    TRADZ  
    Disable time  
    Disable time  
    5
    3
    —
    —
    4-18  
    4-19  
    TDACKS  
    TACKDH  
    Setup time  
    Hold time  
    3
    1
    —
    —
    ns  
    ns  
    4-20  
    4-20  
    4-21  
    4-22  
    TADSS  
    TDSAH  
    TWDS  
    Setup time  
    Hold time  
    3
    1
    5
    —
    —
    —
    ns  
    ns  
    ns  
    4-21  
    4-22  
    4-21  
    4-22  
    Pulse width  
    Time to re-assert  
    TACKREQL  
    1. After second write in 16-bit mode  
    2. After first write in 16-bit mode  
    or after write in 8-bit mode  
    ns  
    ns  
    4-17,  
    4-20  
    4T + 5  
    5
    5T + 9  
    13  
    1. The formulas: T = clock cycle. f ipb = 60MHz, T = 16.7ns.  
    HACK  
    TACKDZ  
    TACKDV  
    HD  
    TACKREQL  
    TREQACKL  
    TACKREQH  
    HREQ  
    Figure 4-17 Controller-to-Host DMA Read Mode  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    37  
    HA  
    TRADX  
    HCS  
    HDS  
    HRW  
    TRADV  
    TRADZ  
    HD  
    Figure 4-18 Single Strobe Read Mode  
    HA  
    TRADX  
    HCS  
    HWR  
    HRD  
    HD  
    TRADZ  
    TRADV  
    Figure 4-19 Dual Strobe Read Mode  
    HACK  
    HD  
    TACKDH  
    TDACKS  
    TACKREQL  
    TREQACKL  
    TACKREQH  
    HREQ  
    Figure 4-20 Host-to-Controller DMA Write Mode  
    56853 Technical Data, Rev. 6  
    38  
    Freescale Semiconductor  
    Host Interface Port  
    HA  
    TDSAH  
    HCS  
    HDS  
    TWDS  
    TDSAH  
    HRW  
    HD  
    TADSS  
    TADSS  
    TDSAH  
    Figure 4-21 Single Strobe Write Mode  
    HA  
    HCS  
    TWDS  
    HWR  
    TDSAH  
    TADSS  
    HRD  
    HD  
    TADSS  
    Figure 4-22 Dual Strobe Write Mode  
    56853 Technical Data, Rev. 6  
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    39  
    4.9 Serial Peripheral Interface (SPI) Timing  
    1
    Table 4-10 SPI Timing  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    = V  
    = 3.0–3.6V, T = –40° to +120°C, C ≤ 50pF, f = 120MHz  
    SS  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA A L op  
    Characteristic  
    Symbol  
    Min  
    Max  
    Unit  
    See Figure  
    Cycle time  
    Master  
    Slave  
    tC  
    4-23, 4-24,  
    4-25, 4-26  
    25  
    25  
    —
    —
    ns  
    ns  
    Enable lead time  
    Master  
    Slave  
    tELD  
    tELG  
    tCH  
    tCL  
    4-26  
    4-26  
    —
    12.5  
    —
    —
    ns  
    ns  
    Enable lag time  
    Master  
    Slave  
    —
    12.5  
    —
    —
    ns  
    ns  
    Clock (SCLK) high time  
    Master  
    Slave  
    ns  
    ns  
    4-23, 4-24,  
    4-25, 4-26  
    9
    12.5  
    —
    —
    Clock (SCLK) low time  
    4-26  
    Master  
    Slave  
    12  
    12.5  
    —
    —
    ns  
    ns  
    Data set-up time required for inputs  
    Master  
    Slave  
    tDS  
    4-23, 4-24,  
    4-25, 4-26  
    10  
    2
    —
    —
    ns  
    ns  
    Data hold time required for inputs  
    Master  
    Slave  
    tDH  
    4-23, 4-24,  
    4-25, 4-26  
    0
    2
    —
    —
    ns  
    ns  
    Access time (time to data active from high-impedance state)  
    Slave  
    tA  
    ns  
    ns  
    4-26  
    4-26  
    5
    2
    15  
    9
    Disable time (hold time to high-impedance state)  
    Slave  
    tD  
    ns  
    ns  
    Data valid for outputs  
    Master  
    Slave (after enable edge)  
    tDV  
    4-23, 4-24,  
    4-25, 4-26  
    —
    —
    2
    14  
    ns  
    ns  
    Data invalid  
    Master  
    Slave  
    tDI  
    tR  
    tF  
    4-23, 4-24,  
    4-25, 4-26  
    0
    0
    —
    —
    ns  
    ns  
    Rise time  
    Master  
    Slave  
    4-23, 4-24,  
    4-25, 4-26  
    —
    —
    11.5  
    10.0  
    ns  
    ns  
    Fall time  
    Master  
    Slave  
    4-23, 4-24,  
    4-25, 4-26  
    —
    —
    9.7  
    9.0  
    ns  
    ns  
    56853 Technical Data, Rev. 6  
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    Freescale Semiconductor  
    Serial Peripheral Interface (SPI) Timing  
    SS  
    (Input)  
    SS is held High on master  
    tC  
    tR  
    tF  
    tCL  
    SCLK (CPOL = 0)  
    (Output)  
    tCH  
    tF  
    tR  
    tCL  
    SCLK (CPOL = 1)  
    (Output)  
    tDH  
    tCH  
    tDS  
    tCH  
    MSB in  
    tDI  
    MISO  
    (Input)  
    Bits 14–1  
    LSB in  
    tDI(ref)  
    tDV  
    MOSI  
    (Output)  
    Master MSB out  
    tF  
    Bits 14–1  
    Master LSB out  
    tR  
    Figure 4-23 SPI Master Timing (CPHA = 0)  
    SS  
    (Input)  
    SS is held High on master  
    tC  
    tF  
    tR  
    tCL  
    SCLK (CPOL = 0)  
    (Output)  
    tCH  
    tF  
    tCL  
    SCLK (CPOL = 1)  
    (Output)  
    tDS  
    tCH  
    tR  
    tDH  
    MISO  
    (Input)  
    MSB in  
    tDI  
    Bits 14–1  
    LSB in  
    tDV(ref)  
    tDV  
    MOSI  
    (Output)  
    Master MSB out  
    tF  
    Bits 14– 1  
    Master LSB out  
    tR  
    Figure 4-24 SPI Master Timing (CPHA = 1)  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    41  
    SS  
    (Input)  
    tC  
    tF  
    tELG  
    tR  
    tCL  
    SCLK (CPOL = 0)  
    (Input)  
    tCH  
    tELD  
    tCL  
    SCLK (CPOL = 1)  
    (Input)  
    tF  
    tA  
    tR  
    tD  
    tCH  
    MISO  
    (Output)  
    Slave MSB out  
    tDH  
    Bits 14–1  
    tDV  
    Slave LSB out  
    tDI  
    tDS  
    tDI  
    MOSI  
    (Input)  
    MSB in  
    Bits 14–1  
    LSB in  
    Figure 4-25 SPI Slave Timing (CPHA = 0)  
    SS  
    (Input)  
    tF  
    tC  
    tR  
    tCL  
    SCLK (CPOL = 0)  
    (Input)  
    tCH  
    tELG  
    tELD  
    tCL  
    SCLK (CPOL = 1)  
    (Input)  
    tDV  
    tR  
    tF  
    tA  
    tCH  
    tD  
    Slave LSB out  
    tDI  
    MISO  
    (Output)  
    Slave MSB out  
    Bits 14–1  
    tDV  
    tDS  
    tDH  
    MOSI  
    (Input)  
    MSB in  
    Bits 14–1  
    LSB in  
    Figure 4-26 SPI Slave Timing (CPHA = 1)  
    56853 Technical Data, Rev. 6  
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    Quad Timer Timing  
    4.10 Quad Timer Timing  
    1, 2  
    Table 4-11 Quad Timer Timing  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    = V  
    = 3.0–3.6V, T = –40° to +120°C, C ≤ 50pF, f = 120MHz  
    SS  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA A L op  
    Characteristic  
    Symbol  
    PIN  
    Min  
    Max  
    —
    Unit  
    ns  
    Timer input period  
    2T + 3  
    1T + 3  
    2T - 3  
    1T - 3  
    Timer input high/low period  
    Timer output period  
    PINHL  
    —
    ns  
    POUT  
    —
    ns  
    Timer output high/low period  
    POUTHL  
    —
    ns  
    1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.  
    2. Parameters listed are guaranteed by design.  
    Timer Inputs  
    PIN  
    PINHL  
    PINHL  
    Timer Outputs  
    POUT  
    POUTHL  
    POUTHL  
    Figure 4-27 Timer Timing  
    4.11 Enhanced Synchronous Serial Interface (ESSI) Timing  
    1
    Table 4-12 ESSI Master Mode Switching Characteristics  
    Operating Conditions: V = V  
    SS  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    = V  
    = 3.0–3.6V, T = –40° to +120°C, C ≤ 50pF, f = 120MHz  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA A L op  
    Parameter  
    Symbol  
    Min  
    Typ  
    Max  
    Units  
    152  
    —
    SCK frequency  
    fs  
    —
    —
    MHz  
    SCK period3  
    tSCKW  
    tSCKH  
    tSCKL  
    66.7  
    —
    —
    —
    ns  
    ns  
    ns  
    33.44  
    SCK high time  
    —
    —
    33.44  
    —
    SCK low time  
    Output clock rise/fall time  
    —
    4
    —
    ns  
    ns  
    Delay from SCK high to SC2 (bl) high - Master5  
    tTFSBHM  
    -1.0  
    —
    1.0  
    56853 Technical Data, Rev. 6  
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    43  
    1
    Table 4-12 ESSI Master Mode Switching Characteristics (Continued)  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    = V  
    = 3.0–3.6V, T = –40° to +120°C, C ≤ 50pF, f = 120MHz  
    SS  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA A L op  
    Parameter  
    Symbol  
    Min  
    Typ  
    Max  
    Units  
    Delay from SCK high to SC2 (wl) high - Master5  
    Delay from SC0 high to SC1 (bl) high - Master5  
    Delay from SC0 high to SC1 (wl) high - Master5  
    Delay from SCK high to SC2 (bl) low - Master5  
    Delay from SCK high to SC2 (wl) low - Master5  
    Delay from SC0 high to SC1 (bl) low - Master5  
    tTFSWHM  
    -1.0  
    —
    1.0  
    ns  
    tRFSBHM  
    tRFSWHM  
    tTFSBLM  
    tTFSWLM  
    tRFSBLM  
    tRFSWLM  
    tTXEM  
    -1.0  
    -1.0  
    -1.0  
    -1.0  
    -1.0  
    -1.0  
    -0.1  
    -0.1  
    -0.1  
    -4  
    —
    —
    —
    —
    —
    —
    —
    —
    —
    —
    —
    —
    1.0  
    1.0  
    1.0  
    1.0  
    1.0  
    1.0  
    2
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    ns  
    Delay from SC0 high to SC1 (wl) low - Master5  
    SCK high to STD enable from high impedance - Master  
    SCK high to STD valid - Master  
    tTXVM  
    2
    SCK high to STD not valid - Master  
    SCK high to STD high impedance - Master  
    SRD Setup time before SC0 low - Master  
    SRD Hold time after SC0 low - Master  
    tTXNVM  
    tTXHIM  
    tSM  
    —
    0
    4
    —
    —
    tHM  
    4
    Synchronous Operation (in addition to standard internal clock parameters)  
    SRD Setup time before SCK low - Master  
    SRD Hold time after SCK low - Master  
    tTSM  
    tTHM  
    4
    4
    —
    —
    —
    —
    ns  
    ns  
    1. Master mode is internally generated clocks and frame syncs  
    2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for an 120MHz part.  
    3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)  
    and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync  
    have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in  
    the tables and in the figures.  
    4. 50 percent duty cycle  
    5. bl = bit length; wl = word length  
    56853 Technical Data, Rev. 6  
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    Enhanced Synchronous Serial Interface (ESSI) Timing  
    tSCKW  
    tSCKH  
    tSCKL  
    SCK output  
    SC2 (bl) output  
    SC2 (wl) output  
    tTFSBHM  
    tTFSBLM  
    tTFSWHM  
    tTFSWLM  
    tTXVM  
    tTXEM  
    tTXNVM  
    tTXHIM  
    First Bit  
    Last Bit  
    STD  
    SC0 output  
    tRFSBHM  
    tRFBLM  
    SC1 (bl) output  
    SC1 (wl) output  
    tRFSWHM  
    tRFSWLM  
    tTSM  
    tSM  
    tHM  
    tTHM  
    SRD  
    Figure 4-28 Master Mode Timing Diagram  
    1
    Table 4-13 ESSI Slave Mode Switching Characteristics  
    Operating Conditions: V = V  
    SS  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    = V  
    = 3.0–3.6V, T = –40° to +120°C, C ≤ 50pF, f = 120MHz  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA A L op  
    Parameter  
    Symbol  
    fs  
    Min  
    —
    Typ  
    —
    Max  
    Units  
    MHz  
    ns  
    152  
    —
    SCK frequency  
    SCK period3  
    tSCKW  
    tSCKH  
    tSCKL  
    66.7  
    —
    33.44  
    SCK high time  
    —
    —
    —
    ns  
    33.44  
    —
    SCK low time  
    —
    ns  
    Output clock rise/fall time  
    —
    4
    —
    ns  
    ns  
    Delay from SCK high to SC2 (bl) high - Slave5  
    tTFSBHS  
    -1  
    —
    29  
    56853 Technical Data, Rev. 6  
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    45  
    1
    Table 4-13 ESSI Slave Mode Switching Characteristics (Continued)  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    = V  
    = 3.0–3.6V, T = –40° to +120°C, C ≤ 50pF, f = 120MHz  
    SS  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA A L op  
    Parameter  
    Symbol  
    tTFSWHS  
    tRFSBHS  
    tRFSWHS  
    tTFSBLS  
    tTFSWLS  
    tRFSBLS  
    tRFSWLS  
    tTXES  
    Min  
    -1  
    -1  
    -1  
    -29  
    -29  
    -29  
    -29  
    —
    4
    Typ  
    —
    —
    —
    —
    —
    —
    —
    —
    —
    —
    —
    —
    —
    —
    —
    Max  
    29  
    29  
    29  
    29  
    29  
    29  
    29  
    15  
    15  
    15  
    15  
    15  
    15  
    —
    Units  
    ns  
    Delay from SCK high to SC2 (wl) high - Slave5  
    Delay from SC0 high to SC1 (bl) high - Slave5  
    Delay from SC0 high to SC1 (wl) high - Slave5  
    Delay from SCK high to SC2 (bl) low - Slave5  
    Delay from SCK high to SC2 (wl) low - Slave5  
    Delay from SC0 high to SC1 (bl) low - Slave5  
    ns  
    ns  
    ns  
    ns  
    ns  
    Delay from SC0 high to SC1 (wl) low - Slave5  
    ns  
    SCK high to STD enable from high impedance - Slave  
    ns  
    SCK high to STD valid - Slave  
    tTXVS  
    ns  
    SC2 high to STD enable from high impedance (first bit) - Slave  
    SC2 high to STD valid (first bit) - Slave  
    SCK high to STD not valid - Slave  
    tFTXES  
    tFTXVS  
    tTXNVS  
    tTXHIS  
    4
    ns  
    4
    ns  
    4
    ns  
    SCK high to STD high impedance - Slave  
    SRD Setup time before SC0 low - Slave  
    SRD Hold time after SC0 low - Slave  
    4
    ns  
    tSS  
    4
    ns  
    tHS  
    4
    —
    ns  
    Synchronous Operation (in addition to standard external clock parameters)  
    SRD Setup time before SCK low - Slave  
    SRD Hold time after SCK low - Slave  
    tTSS  
    tTHS  
    4
    4
    —
    —
    —
    —
    ns  
    ns  
    1. Slave mode is externally generated clocks and frame syncs  
    2. Max clock frequency is IP_clk/4 = 60MHz / 4 = 15MHz for a 120MHz part.  
    3. All the timings for the ESSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)  
    and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync  
    have been inverted, all the timings remain valid by inverting the clock signal SCK/SC0 and/or the frame sync SC2/SC1 in  
    the tables and in the figures.  
    4. 50 percent duty cycle  
    5. bl = bit length; wl = word length  
    56853 Technical Data, Rev. 6  
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    Freescale Semiconductor  
    Serial Communication Interface (SCI) Timing  
    tSCKW  
    tSCKH  
    tSCKL  
    SCK input  
    SC2 (bl) input  
    SC2 (wl) input  
    tTFSBLS  
    tTFSBHS  
    tTFSWHS  
    tTFSWLS  
    tFTXVS  
    tFTXES  
    tTXVS  
    tTXNVS  
    tTXES  
    tTXHIS  
    First Bit  
    Last Bit  
    STD  
    SC0 input  
    tRFBLS  
    tRFSBHS  
    SC1 (bl) input  
    SC1 (wl) input  
    tRFSWHS  
    tRFSWLS  
    tTSS  
    tSS  
    tHS  
    tTHS  
    SRD  
    Figure 4-29 Slave Mode Clock Timing  
    4.12 Serial Communication Interface (SCI) Timing  
    4
    Table 4-14 SCI Timing  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    DD  
    = V  
    = 3.0–3.6V, T = –40  
    °
    to +120  
    °
    C, C ≤  
    50pF, f = 120MHz  
    op  
    SS  
    SSIO  
    SSA  
    DDIO  
    DDA  
    A
    L
    Characteristic  
    Symbol  
    Min  
    Max  
    Unit  
    Baud Rate1  
    BR  
    —
    (fMAX)/(32)  
    1.04/BR  
    Mbps  
    RXD2 Pulse Width  
    TXD3 Pulse Width  
    RXDPW  
    TXDPW  
    0.965/BR  
    0.965/BR  
    ns  
    ns  
    1.04/BR  
    1. fMAX is the frequency of operation of the system clock in MHz.  
    2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.  
    3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.  
    4. Parameters listed are guaranteed by design.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    47  
    RXD  
    SCI receive  
    data pin  
    RXDPW  
    (Input)  
    Figure 4-30 RXD Pulse Width  
    TXD  
    SCI receive  
    data pin  
    TXDPW  
    (Input)  
    Figure 4-31 TXD Pulse Width  
    4.13 JTAG Timing  
    1, 3  
    Table 4-15 JTAG Timing  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    = V  
    = 3.0–3.6V, T = –40  
    °
    to +120  
    °
    C, C ≤  
    50pF, f = 120MHz  
    op  
    SS  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA  
    A
    L
    Characteristic  
    TCK frequency of operation2  
    Symbol  
    fOP  
    Min  
    Max  
    30  
    —
    Unit  
    MHz  
    ns  
    DC  
    33.3  
    16.6  
    3
    TCK cycle time  
    tCY  
    TCK clock pulse width  
    TMS, TDI data setup time  
    TMS, TDI data hold time  
    TCK low to TDO data valid  
    TCK low to TDO tri-state  
    TRST assertion time  
    DE assertion time  
    tPW  
    —
    ns  
    tDS  
    —
    ns  
    tDH  
    3
    —
    ns  
    tDV  
    —
    12  
    10  
    —
    ns  
    tTS  
    —
    ns  
    tTRST  
    tDE  
    35  
    4T  
    ns  
    —
    ns  
    1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 120MHz  
    operation, T = 8.33ns.  
    2. TCK frequency of operation must be less than 1/4 the processor rate.  
    3. Parameters listed are guaranteed by design.  
    56853 Technical Data, Rev. 6  
    48  
    Freescale Semiconductor  
    JTAG Timing  
    tCY  
    tPW  
    tPW  
    VIH  
    VM  
    VIL  
    VM  
    TCK  
    (Input)  
    VM = VIL + (VIH – VIL)/2  
    Figure 4-32 Test Clock Input Timing Diagram  
    TCK  
    (Input)  
    tDS  
    tDH  
    TDI  
    TMS  
    Input Data Valid  
    (Input)  
    tDV  
    TDO  
    (Output)  
    Output Data Valid  
    tTS  
    TDO  
    (Output)  
    Figure 4-33 Test Access Port Timing Diagram  
    TRST  
    (Input)  
    tTRST  
    Figure 4-34 TRST Timing Diagram  
    DE  
    tDE  
    Figure 4-35 Enhanced OnCE—Debug Event  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    49  
    4.14 GPIO Timing  
    1, 2  
    Table 4-16 GPIO Timing  
    Operating Conditions: V = V  
    = V  
    = 0 V, V = 1.62-1.98V, V  
    = V  
    = 3.0–3.6V, T = –40  
    °
    to +120  
    °
    C, C ≤  
    50pF, f = 120MHz  
    op  
    SS  
    SSIO  
    SSA  
    DD  
    DDIO  
    DDA  
    A
    L
    Characteristic  
    Symbol  
    PIN  
    Min  
    Max  
    —
    Unit  
    ns  
    GPIO input period  
    2T + 3  
    1T + 3  
    2T - 3  
    1T - 3  
    GPIO input high/low period  
    GPIO output period  
    PINHL  
    —
    ns  
    POUT  
    —
    ns  
    GPIO output high/low period  
    POUTHL  
    —
    ns  
    1. In the formulas listed, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns  
    2. Parameters listed are guaranteed by design.  
    GPIO Inputs  
    PIN  
    PINHL  
    PINHL  
    GPIO Outputs  
    POUT  
    POUTHL  
    POUTHL  
    Figure 4-36 GPIO Timing  
    56853 Technical Data, Rev. 6  
    50  
    Freescale Semiconductor  
    Package and Pin-Out Information 56853  
    Part 5 Packaging  
    5.1 Package and Pin-Out Information 56853  
    This section contains package and pin-out information for the 128-pin LQFP configuration of the 56853.  
    PIN 65  
    V
    V
    V
    V
    A15  
    A14  
    HDS  
    HCS  
    HREQ  
    HACK  
    D6  
    DD  
    PIN 103  
    SS  
    SSIO  
    DDIO  
    D7  
    D8  
    D9  
    D10  
    A13  
    A12  
    V
    SSIO  
    V
    V
    DDIO  
    DD  
    V
    TCK  
    TMS  
    TDI  
    SS  
    V
    V
    DDIO  
    SSIO  
    TDO  
    TRST  
    DE  
    STD0  
    SRD0  
    SCK0  
    SC00  
    SC01  
    SC02  
    V
    SS  
    V
    DD  
    A11  
    A10  
    A9  
    A8  
    V
    D11  
    D12  
    V
    DDIO  
    V
    SSIO  
    SSIO  
    D13  
    D14  
    ORIENTATION  
    MARK  
    V
    DDIO  
    HD7  
    HD6  
    PIN 39  
    D15  
    PIN 1  
    Figure 5-1 Top View, 56853 128-pin LQFP Package  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    51  
    Table 5-1 56853 Pin Identification by Pin Number  
    Pin No.  
    Signal Name  
    Pin No. Signal Name Pin No.  
    Signal Name  
    Pin No.  
    Signal Name  
    1
    2
    3
    4
    MISO  
    MOSI  
    SCK  
    SS  
    33  
    34  
    35  
    36  
    CLKO  
    RSTO  
    RESET  
    HD3  
    65  
    66  
    67  
    68  
    RXD0  
    TXDO  
    A16  
    97  
    98  
    TIO3  
    TIO2  
    TIO1  
    99  
    A17  
    100  
    V
    DDIO  
    5
    6
    V
    37  
    38  
    HD4  
    HD5  
    69  
    70  
    A18  
    A19  
    A20  
    101  
    102  
    TIO0  
    DDIO  
    V
    V
    SSIO  
    SSIO  
    HDS  
    HCS  
    7
    8
    RD  
    39  
    40  
    HD6  
    HD7  
    71  
    72  
    103  
    104  
    WR  
    V
    DDIO  
    9
    A0  
    A1  
    41  
    42  
    V
    73  
    74  
    D0  
    105  
    106  
    HREQ  
    HACK  
    DDIO  
    10  
    V
    V
    SSIO  
    SSIO  
    11  
    12  
    13  
    A2  
    A3  
    43  
    44  
    45  
    A8  
    75  
    76  
    77  
    CS0  
    CS1  
    CS2  
    107  
    108  
    109  
    D6  
    D7  
    D8  
    A9  
    V
    A10  
    A11  
    DD  
    14  
    15  
    16  
    17  
    18  
    19  
    V
    46  
    47  
    48  
    49  
    50  
    51  
    78  
    79  
    80  
    81  
    82  
    83  
    CS3  
    110  
    111  
    112  
    113  
    114  
    115  
    D9  
    SS  
    MODA  
    MODB  
    MODC  
    V
    V
    V
    D10  
    DD  
    DD  
    DD  
    V
    V
    DD  
    SS  
    DE  
    V
    V
    SS  
    SS  
    V
    TRST  
    TDO  
    HA0  
    HA1  
    V
    DDIO  
    DDIO  
    V
    V
    SSIO  
    SSIO  
    20  
    21  
    22  
    IRQA  
    IRQB  
    52  
    53  
    54  
    TDI  
    TMS  
    TCK  
    84  
    85  
    86  
    HA2  
    HRWB  
    D1  
    116  
    117  
    118  
    STD0  
    SRD0  
    SCK0  
    V
    DDA  
    23  
    24  
    V
    55  
    56  
    V
    87  
    88  
    D2  
    D3  
    119  
    120  
    SC00  
    SC01  
    SSA  
    DDIO  
    XTAL  
    V
    SSIO  
    25  
    26  
    27  
    EXTAL  
    A4  
    57  
    58  
    59  
    A12  
    A13  
    A14  
    89  
    90  
    91  
    D4  
    D5  
    121  
    122  
    123  
    SC02  
    D11  
    A5  
    V
    V
    D12  
    DDIO  
    DDIO  
    28  
    29  
    30  
    31  
    32  
    A6  
    A7  
    60  
    61  
    62  
    63  
    64  
    A15  
    92  
    93  
    94  
    95  
    96  
    124  
    125  
    126  
    127  
    128  
    V
    DDIO  
    V
    V
    V
    SSIO  
    DDIO  
    SSIO  
    HD0  
    HD1  
    HD2  
    V
    RXD1  
    TXD1  
    D13  
    D14  
    D15  
    SSIO  
    V
    SS  
    V
    V
    SS  
    DD  
    56853 Technical Data, Rev. 6  
    52  
    Freescale Semiconductor  
    Package and Pin-Out Information 56853  
    102  
    65  
    64  
    103  
    128  
    39  
    38  
    MILLIMETERS  
    DIM  
    MIN  
    ---  
    MAX  
    1.60  
    0.15  
    1.45  
    0.27  
    0.23  
    0.20  
    0.16  
    A
    A1  
    A2  
    b
    b1  
    c
    0.05  
    1.35  
    0.17  
    0.17  
    0.09  
    0.09  
    NOTES:  
    1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M,  
    1994.  
    2. CONTROLLING DIMENSION: MILLIMETER.  
    3. DATUM PLANE H IS LOCATED AT BOTTOM OF LEAD AND IS  
    COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE  
    PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE.  
    4. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE  
    H.  
    c1  
    D
    22.00 BSC  
    D1  
    e
    E
    E1  
    L
    L1  
    L2  
    S
    20.00BSC  
    0.50 BSC  
    16.00 BSC  
    14.00 BSC  
    5. DIMENSIONS D AND E TO BE DETERMINED AT SEATING  
    PLANE C.  
    6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD  
    PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE.  
    DIMENSIONS D1 AND E1 DO INCLUDE MOLD MISMATCH  
    AND ARE DETERMINED AT DATUM PLANE H.  
    7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.  
    DAMBAR PROTRUSION SHALL NOT CAUSE THE b  
    DIMENSION TO EXCEED 0.35.  
    0.45  
    0.75  
    1.00 REF  
    0.50 REF  
    0.20  
    0.08  
    ---  
    ---  
    R1  
    R2  
    0
    0.08  
    0.20  
    7o  
    ---  
    0o  
    0o  
    01  
    02  
    11o  
    13o  
    Case Outline - 1129-01  
    Figure 5-2 128-pin LQFP Mechanical Information  
    Please see www.freescale.com for the most current case outline.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    53  
    Part 6 Design Considerations  
    6.1 Thermal Design Considerations  
    An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:  
    Equation 1: TJ = TA + (PD x RθJA  
    )
    Where:  
    TA = ambient temperature °C  
    RθJA = package junction-to-ambient thermal resistance °C/W  
    PD = power dissipation in package  
    Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a  
    case-to-ambient thermal resistance:  
    Equation 2: RθJA = RθJC + RθCA  
    Where:  
    RθJA = package junction-to-ambient thermal resistance °C/W  
    RθJC = package junction-to-case thermal resistance °C/W  
    RθCA = package case-to-ambient thermal resistance °C/W  
    RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change  
    the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around the device, add  
    a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal  
    dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages  
    with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient  
    environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an  
    alternate path through the PCB, analysis of the device thermal performance may need the additional modeling  
    capability of a system level thermal simulation tool.  
    The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package  
    is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the thermal  
    performance is adequate, a system level model may be appropriate.  
    A complicating factor is the existence of three common definitions for determining the junction-to-case thermal  
    resistance in plastic packages:  
    •
    Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the  
    chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation  
    across the surface.  
    •
    •
    Measure the thermal resistance from the junction to where the leads are attached to the case. This definition  
    is approximately equal to a junction to board thermal resistance.  
    Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package case  
    determined by a thermocouple.  
    As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first  
    definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a  
    case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case  
    56853 Technical Data, Rev. 6  
    54  
    Freescale Semiconductor  
    Electrical Design Considerations  
    thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will  
    estimate a junction temperature slightly hotter than actual. Hence, the new thermal metric, Thermal Characterization  
    Parameter, or ΨJT, has been defined to be (TJ – TT)/PD. This value gives a better estimate of the junction temperature  
    in natural convection when using the surface temperature of the package. Remember that surface temperature  
    readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface  
    and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple  
    wire and bead to the top center of the package with thermally conductive epoxy.  
    6.2 Electrical Design Considerations  
    CAUTION  
    This device contains protective circuitry to guard against  
    damage due to high static voltage or electrical fields.  
    However, normal precautions are advised to avoid  
    application of any voltages higher than maximum rated  
    voltages to this high-impedance circuit. Reliability of  
    operation is enhanced if unused inputs are tied to an  
    appropriate voltage level.  
    Use the following list of considerations to assure correct operation:  
    •
    Provide a low-impedance path from the board power supply to each VDD pin on the device, and from the  
    board ground to each VSS (GND) pin.  
    •
    The minimum bypass requirement is to place six 0.01–0.1 μF capacitors positioned as close as possible to  
    the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each  
    of the ten VDD/VSS pairs, including VDDA/VSSA.  
    •
    Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS (GND)  
    pins are less than 0.5 inch per capacitor lead.  
    •
    •
    Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and GND.  
    Bypass the VDD and GND layers of the PCB with approximately 100 μF, preferably with a high-grade  
    capacitor such as a tantalum capacitor.  
    •
    •
    Because the device’s output signals have fast rise and fall times, PCB trace lengths should be minimal.  
    Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.  
    This is especially critical in systems with higher capacitive loads that could create higher transient currents  
    in the VDD and GND circuits.  
    •
    •
    All inputs must be terminated (i.e., not allowed to float) using CMOS levels.  
    Take special care to minimize noise levels on the VDDA and VSSA pins.  
    •
    When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    55  
    •
    •
    Designs that utilize the TRST pin for JTAG port or Enhance OnCE module functionality (such as  
    development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as  
    well as a means to assert TRST independently of RESET. Designs that do not require debugging  
    functionality, such as consumer products, should tie these pins together.  
    The internal POR (Power on Reset) will reset the part at power on with reset asserted or pulled high but  
    requires that TRST be asserted at power on.  
    56853 Technical Data, Rev. 6  
    56  
    Freescale Semiconductor  
    Electrical Design Considerations  
    Part 7 Ordering Information  
    Table 7-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor  
    sales office or authorized distributor to determine availability and to order parts.  
    Table 7-1 56853 Ordering Information  
    Supply  
    Voltage  
    Pin  
    Count  
    Frequency  
    (MHz)  
    Part  
    Package Type  
    Order Number  
    DSP56853  
    1.8V, 3.3V  
    1.8V, 3.3V  
    Low-Profile Quad Flat Pack (LQFP)  
    128  
    128  
    120  
    120  
    DSP56853FG120  
    DSP56853  
    Low-Profile Quad Flat Pack (LQFP)  
    DSP56853FGE *  
    *This package is RoHS compliant.  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    57  
    56853 Technical Data, Rev. 6  
    58  
    Freescale Semiconductor  
    Electrical Design Considerations  
    56853 Technical Data, Rev. 6  
    Freescale Semiconductor  
    59  
    How to Reach Us:  
    Home Page:  
    www.freescale.com  
    E-mail:  
    support@freescale.com  
    USA/Europe or Locations Not Listed:  
    Freescale Semiconductor  
    Technical Information Center, CH370  
    1300 N. Alma School Road  
    Chandler, Arizona 85224  
    +1-800-521-6274 or +1-480-768-2130  
    support@freescale.com  
    Europe, Middle East, and Africa:  
    Freescale Halbleiter Deutschland GmbH  
    Technical Information Center  
    Schatzbogen 7  
    81829 Muenchen, Germany  
    +44 1296 380 456 (English)  
    +46 8 52200080 (English)  
    +49 89 92103 559 (German)  
    +33 1 69 35 48 48 (French)  
    support@freescale.com  
    Japan:  
    Freescale Semiconductor Japan Ltd.  
    Headquarters  
    ARCO Tower 15F  
    1-8-1, Shimo-Meguro, Meguro-ku,  
    Tokyo 153-0064, Japan  
    0120 191014 or +81 3 5437 9125  
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    Information in this document is provided solely to enable system and  
    software implementers to use Freescale Semiconductor products. There are  
    no express or implied copyright licenses granted hereunder to design or  
    fabricate any integrated circuits or integrated circuits based on the  
    information in this document.  
    Asia/Pacific:  
    Freescale Semiconductor Hong Kong Ltd.  
    Technical Information Center  
    2 Dai King Street  
    Tai Po Industrial Estate  
    Tai Po, N.T., Hong Kong  
    +800 2666 8080  
    Freescale Semiconductor reserves the right to make changes without further  
    notice to any products herein. Freescale Semiconductor makes no warranty,  
    representation or guarantee regarding the suitability of its products for any  
    particular purpose, nor does Freescale Semiconductor assume any liability  
    arising out of the application or use of any product or circuit, and specifically  
    disclaims any and all liability, including without limitation consequential or  
    incidental damages. “Typical” parameters that may be provided in Freescale  
    Semiconductor data sheets and/or specifications can and do vary in different  
    applications and actual performance may vary over time. All operating  
    parameters, including “Typicals”, must be validated for each customer  
    application by customer’s technical experts. Freescale Semiconductor does  
    not convey any license under its patent rights nor the rights of others.  
    Freescale Semiconductor products are not designed, intended, or authorized  
    for use as components in systems intended for surgical implant into the body,  
    or other applications intended to support or sustain life, or for any other  
    application in which the failure of the Freescale Semiconductor product could  
    create a situation where personal injury or death may occur. Should Buyer  
    purchase or use Freescale Semiconductor products for any such unintended  
    or unauthorized application, Buyer shall indemnify and hold Freescale  
    Semiconductor and its officers, employees, subsidiaries, affiliates, and  
    distributors harmless against all claims, costs, damages, and expenses, and  
    reasonable attorney fees arising out of, directly or indirectly, any claim of  
    personal injury or death associated with such unintended or unauthorized  
    use, even if such claim alleges that Freescale Semiconductor was negligent  
    regarding the design or manufacture of the part.  
    support.asia@freescale.com  
    For Literature Requests Only:  
    Freescale Semiconductor Literature Distribution Center  
    P.O. Box 5405  
    Denver, Colorado 80217  
    1-800-441-2447 or 303-675-2140  
    Fax: 303-675-2150  
    LDCForFreescaleSemiconductor@hibbertgroup.com  
    Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor,  
    Inc. All other product or service names are the property of their respective owners.  
    This product incorporates SuperFlash® technology licensed from SST.  
    © Freescale Semiconductor, Inc. 2005. All rights reserved.  
    DSP56853  
    Rev. 6  
    01/2007  

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