56855 General Description
• 120 MIPS at 120MHz
• 24K x 16-bit Program SRAM
• 24K x 16-bit Data SRAM
• 1K x 16-bit Boot ROM
• Access up to 2M words of program memory or 8M
words of data memory
• Chip Select Logic for glueless interface to ROM and
SRAM
• Six (6) independent channels of DMA
• Enhanced Synchronous Serial Interface (ESSI)
• Two (2) Serial Communication Interfaces (SCI)
• General Purpose 16-bit Quad Timer with 1 external pin
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Computer Operating Properly (COP)/Watchdog Timer
• Time-of-Day (TOD)
• 100 LQFP package
• Up to 18 GPIO
6
V
DDIO
10
V
DD
4
V
SSIO
10
V
SS
V
DDA
4
V
SSA
JTAG/
Enhanced
OnCE
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
16-Bit
DSP56800E Core
Data ALU
16 x 16 + 36
→
36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
Memory
Program Memory
24,576 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
24,576 x 16 SRAM
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
System
Bus
Control
DMA
6 channel
Core CLK
IPBus Bridge (IPBB)
IPWDB
Decoding
Peripherals
A0-20 [20:0]
D0-D15 [15:0]
RD Enable
WR Enable
CS0-CS3[3:0] or
GPIOA0-GPIOA3[3:0]
Bus Control
External Address
Bus Switch
External Data
Bus Switch
External Bus
Interface Unit
2 SCI ESSI0
or
or
GPIOE GPIOC
IPRDB
IPAB
DMA Requests
IPBus CLK
POR
3
CLKO
MODEA-C or
(GPIOH0-H2)
RSTO
RESET
System
COP/TOD CLK Integration
Module
Quad
Timer
or
GPIOG
Interrupt
Controller
COP/
Watch-
dog
Time
of
Day
Clock
Generator
OSC PLL
EXTAL
XTAL
4
6
IRQA
IRQB
56855 Block Diagram
56855 Technical Data, Rev. 6
Freescale Semiconductor
3
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
