MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual D-Type Flip-Flop
with Set and Reset
The MC74VHC74 is an advanced high speed CMOS D–type flip–flop
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The signal level applied to the D input is transferred to Q output during the
positive going transition of the Clock pulse.
Reset (RD) and Set (SD) are independent of the Clock (CP) and are
accomplished by setting the appropriate input Low.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
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High Speed: fmax = 170MHz (Typ) at VCC = 5V
Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2V to 5.5V Operating Range
Low Noise: VOLP = 0.8V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 128 FETs or 32 Equivalent Gates
MC74VHC74
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
DT SUFFIX
14–LEAD TSSOP PACKAGE
CASE 948G–01
M SUFFIX
14–LEAD SOIC EIAJ PACKAGE
CASE 965–01
ORDERING INFORMATION
MC74VHCXXD
MC74VHCXXDT
MC74VHCXXM
SOIC
TSSOP
SOIC EIAJ
LOGIC DIAGRAM
RD1
D1
CP1
SD1
1
2
3
4
5
6
RD2
Q1
Q1
D2
CP2
SD2
13
12
11
10
9
8
Q2
PIN ASSIGNMENT
Q2
RD1
D1
CP1
SD1
Q1
Q1
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VCC
RD2
D2
CP2
SD2
Q2
Q2
FUNCTION TABLE
Inputs
SD
L
H
L
H
H
H
H
H
RD
H
L
L
H
H
H
H
H
CP
X
X
X
D
X
X
X
H
L
X
X
X
Outputs
Q
Q
H
L
L
H
H*
H*
H
L
L
H
No Change
No Change
No Change
GND
L
H
* Both outputs will remain high as long as Set and Reset are low, but the output
states are unpredictable if Set and Reset go high simultaneously.
6/97
©
Motorola, Inc. 1997
1
REV 1
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
