FUNCTIONAL DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
operation, or shuts down after a failure to regain normal
operation.
changed via I2C at any time after power up has successfully
completed.
• A hard over-current limit (short-circuit limit) that is higher
than the cycle by cycle limit at which the device reacts by
shutting down the output immediately. This is necessary to
prevent damage in case of a short-circuit. After that, only
GrpB will attempt a one time retry after a time-out period of
10 ms and will go through a new soft start cycle
Phase Control
REG1 to REG5 use the main Switching frequency FSW1,
which is configured through the FREQ terminal at power up.
FSW1 uses 4 different phases of switching (clock is 80
degrees out of phase) to spread out the current draw by the
individual converters from the input supply over time to
reduce the peak input current demand. The remaining
regulators use FSW2 which can be programmed at any time
via I2C after a successful power up sequence.
Output Over-voltage/Under-voltage Monitoring
In the case of an output over-voltage/under-voltage, the
user has two options that can be programmed through the
I2C interface:
Fault Register
Response A: The output will switch off automatically and
the 34704 would alert the processor through I2C that such an
event happened.
The 34704 has a dedicate fault register accessible via I2C
which indicate which regulator is detecting a fault situation. In
addition to this, each channel has its own fault register which
indicates the type of fault detected in that regulator.
Response B: The output will not switch off. Rather the
34704 communicates to the processor that an over-voltage/
under-voltage condition has occurred and waits for the
processor decision to either shutoff or not; in the mean time
the control loop will try to fix itself.
I2C communication and Registers
The 34704 can communicate using a standard I2C,
communication protocol or an accurate I2C protocol. During
the first one, the device processes the given command as
soon as it has received it. During the accurate data
communication, the device requires that each read/write
command be sent twice to validate the data. The 34704
provides a user accessible register map that allows various
general IC configurations as well as independent control of
each regulator, including fault flag registers and all
configurable features for each regulator.
NOTE: If Response A is set on any of the regulators from
GrpB, and a OV/UV event occurs in the correspondig
regulator, the complete device will shutdown and try to restart
as long as the OV/UV is no longer present. This will also set
the RST signal low until REG2, 3 and 4 are on regulation.
LOGIC AND CONTROL
Startup Sequencing
At power up, the VG regulator starts ramping up in peak
detect mode. Meanwhile, VDDI is tracking VG until it reaches
regulation and releases a POR signal that enables the
internal circuitry and reads the FREQ and SS configuration to
ramp up REG2, REG3 and REG4, that serve as the MPU
main power supplies. Once the MPU is up, I2C
communication is available to enable or disable GrpA, GrpC,
GrpD and GrpE. An extra sequence can be configured for
REG5, REG6 and REG7, changing the order in which they
ramp up when enabled. See Power-Up Sequence on page
28.
OUTPUT GROUPS - REGULATORS
The 34704 is divided in 5 different groups which are
arranged as follows:
• GrpA: Includes REG1(26) (VOUT1)
• GrpB: Includes REG2, REG3, and REG4
• GrpC: Includes REG5, REG6(26), and REG7(26)
• GrpD: Includes REG8
• GrpE: This is a special group. It includes REG5 when
GrpC/E power sequencing option#1 is chosen
Turning on/off each group would cause all contained
regulators to turn on/off.
Soft Start Control
During power up the 34704 reads the SS terminal to
configure a default soft start timing for all regulators when
these are enabled. Soft start for REG5 to REG8 can be
Notes
26. Only on 34704A
34704
Analog Integrated Circuit Device Data
Freescale Semiconductor
21
FREESCALE [ Freescale ]
