TYPICAL APPLICATIONS
.
1
----------------------------------------------------------------------------------------
R2 = VRef
×
Gain
[dB]
(V + IO × RL) – VRef
--------O----------------------------------------------- + -------------------------
R4 R1
VO – VRef
20
f
LC
f
z(c)
Where VRef is the buck regulator reference voltage
(VRef = 0.8 V typ.) at the INV pin,
f
BW
0
VO is the selected output voltage,
f
f
z(ESR) p(FF)
IO is the output load current,
RL is the DC resistance of the inductor L.
f
p(c)
-20
It is apparent that the buck regulator output voltage is
affected by the voltage drop caused by the inductor serial
resistance and the regulator output current. In those
applications which do not require precise output voltage,
setting the formula for calculating selected output voltage can
be simplified as follows:
-40
-180
Phase
[Deg.]
1
--------------------------------------------------------------
R2 = VRef
×
(R1 + R4)
-------------------------
(VO – VRef) ×
R1 × R4
-2 70
Linear Regulator Output Voltage
Φm
The output voltage of the linear regulator (LDO) can be set
by a simple resistor divider according to the following formula:
RU
⎛
⎞
⎠
VLDO = VRef × 1 + -------
⎝
RL
-3 60
1.0
10
100
1000
10000
Frequency [kHz]
Where VRef is the linear regulator reference voltage
(VRef = 0.8 V typ.) at the LFB pin,
Figure 30. Buck Control Loop Bode Plot
The frequency of the zero created by the ESR of the output
VLDO is the LDO selected output voltage,
RU is the “upper” resistor of the LDO resistor divider,
RL is the “lower” resistor of the LDO resistor divider.
capacitor CO is calculated as:
Figure 31 describes the 34701 linear regulator circuit with
the resistor divider RU, RL setting the output voltage VLDO.
1
fz(ESR) = --------------------------
2πCOESR
Where CO is the value of the buck regulator output
capacitor, and ESR is the equivalent series resistance of the
output capacitor.
2.8 V to 6.0 V Input
MC34701
VIN1
The frequency of the compensating network pole can be
calculated as follows:
LDRV
CS
1
fp(c) = ----------------------------------------
V
R
LDO
S
R1R3
-------------------------
LDO
LFB
2πC2
R
(R1 + R3)
C
U
LDO
The well designed and compensated buck regulator
should yield at least 45 deg. phase margin Φm of its overall
loop as depicted in the Figure 30, page 31.
R
L
LCMP
LDO
Compensation
Selecting Buck Regulator Output Voltage
The 34701 buck regulator output voltage can be set by
selecting the right value of the resistors R1, R2 and R4, and
can be determined from the following formula (see Figure 29,
page 30 for the component references):
Figure 31. 34701Linear Regulator Circuit
34701
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
FREESCALE [ Freescale ]
