INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
VPWR
VIC
Internal
Regulator
Over-voltage
Protection
IUP
CS
SO
Programmable
Switch Delay
0–525 ms
Selectable Slew
Rate Gate Drive
SPI
3.0 MHz
HS
Selectable Over-current
SI
SCLK
FS
High Detection
150 A or 100 A
Logic
IN
Selectable Over-
current Low Detection
Blanking Time
Selectable
Overcurrent
Low Detection
15–50 A
RST
WAKE
0.15–155 ms
Open Load
Detection
IDWN
RDWN
Over-temperature
Detection
VIC
Selectable
Output Current
Recopy
Programmable
Watchdog
310–2500 ms
IUP
1/5400 or 1/40000
FSI
GND
CSNS
Figure 2. 33982 Simplified Internal Block Diagram
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
3