FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
The 33982 has four operating modes: Sleep, Normal,
Fault, and Fail-safe. Table 6 summarizes details contained in
succeeding paragraphs.
transitions from Logic [0] to Logic [1]. The WAKE input is
capable of being pulled up to VPWR with a series of limiting
resistance that limits the internal clamp current.
The watchdog timeout is a multiple of an internal oscillator
and is specified in Table 15. As long as the WD bit (D7) of an
incoming SPI message is toggled within the minimum
watchdog timeout period (WDTO), based on the
programmed value of the WDR the device will operate
normally. If an internal watchdog timeout occurs before the
WD bit, the device will revert to a Fail-safe mode until the
device is reinitialized.
Table 6. Fail-safe Operation and Transitions to Other
33982 Modes
Mode
FS WAKE RST WDTO
Comments
Device is in Sleep mode.
All outputs are OFF.
Sleep
x
0
x
0
1
x
Normal mode. Watchdog
is active if enabled.
Normal
Fault
1
No
No
During the Fail-safe mode, the output will be ON or OFF
depending upon the resistor RFS connected to the FSI pin,
regardless of the state of the various direct inputs and modes
(Table 7). In this mode, the SPI register content is retained
except for over-current high and low detection levels and
timing, which are reset to their default value (SOCL, SOCH,
OCLT). The watchdog, over-voltage, over-temperature, and
over-current circuitry (with default value for this one) are fully
operational.
The device is currently in
Fault mode. The faulted
output is OFF.
0
0
1
x
x
1
Watchdog has timed out
and the device is in Fail-
safe mode. The output is
as configured with the
RFS resistor connected
to FSI. RST and WAKE
must be transitioned to
Logic [0] simultaneously
to bring the device out of
the Fail-safe mode or
momentarily tied the FSI
pin to ground.
1
1
1
1
0
1
0
1
1
1
1
0
Fail-
safe
Table 7. Output State During Fail-safe Mode
Yes
RFS (kΩ)
High Side State
0
Fail-safe Mode Disabled
HS OFF
10
30
HS ON
x = Don’t care.
The Fail-safe mode can be detected by monitoring the
WDTO bit D2 of the WDR register. This bit is Logic [1] when
the device is in Fail-safe mode. The device can be brought
out of the Fail-safe mode by transitioning the WAKE and RST
pins from Logic [1] to Logic [0] or forcing the FSI pin to
Logic [0]. Table 6 summarizes the various methods for
resetting the device from the latched Fail-safe mode.
SLEEP MODE
The default mode of the 33982 is the Sleep mode. This is
the state of the device after first applying battery voltage
(VPWR), prior to any I/O transitions. This is also the state of
the device when the WAKE and RST are both Logic [0]. In the
Sleep mode, the output and all unused internal circuitry, such
as the internal 5.0 V regulator, are off to minimize current
draw. In addition, all SPI-configurable features of the device
are as if set to Logic [0]. The device will transition to the
Normal or Fail-safe operating modes based on the WAKE
and RST inputs as defined in Table 6.
If the FSI pin is tied to GND, the Watchdog Fail-safe
operation is disabled.
LOSS OF VDD
If the external 5.0 V supply is not within specification, or
even disconnected, all register content is reset. The output
can still be driven by the direct input IN. The 33982 uses the
battery input to power the output MOSFET related current
sense circuitry, and any other internal Logic, providing fail-
safe device operation with no VDD supplied. In this state, the
watchdog, over-voltage, over-temperature, and over-current
circuitry are fully operational with default values. Current
recopy is active with the default current recopy value.
NORMAL MODE
The 33982 is in Normal mode when:
• VPWR is within the normal voltage range.
•
RST pin is Logic [1].
• No fault has occurred.
FAIL-SAFE MODE AND WATCHDOG
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or RST input pin
33982
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
FREESCALE [ Freescale ]
