ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
TIMING DIAGRAMS
V
IN
RST
t
0.2 V
DD
WRST
t
CS
V
IL
CS
0.7 V
DD
t
LEAD
0.7 V
DD
0.2 V
DD
SCLK
t
SISU
SI
Don’t Care
0.7 V
DD
V
IH
V
IL
t
RSI
t
LAG
V
IH
t
FIS
t
SI(HOLD)
Don’t Care
Valid
Don’t Care
0.7 V
DD
0.2 V
DD
Valid
Figure 4. Input Timing Switching Characteristics
t
RSI
3.5V
t
FIS
V
OH
50%
1.0V
V
OL
SCLK
t
SO(EN)
0.7
V
DD
V
OH
SO
Low-to-High
0.2
V
DD
t
RSO
t
VALID
t
RSO
0.7
V
DD
V
OL
SO
High-to-Low
V
OH
0.2
V
DD
t
SO(DIS)
V
OL
Figure 5. Valid Data Delay Time and Valid Time Waveforms
33977
Analog Integrated Circuit Device Data
Freescale Semiconductor
9