INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
5.0 V
V
PWR
V
PWR
16.0
mA
SP0
SP1
SP2
SP3
SP4
SP5
SP6
SP7
16.0
mA
To
+
2.0 4.0V
–
SPI
mA Ref
Comparator
5.0V
V
PWR
5.0 V
To
+
4.0 V
–
SPI
Ref
Comparator
WAKE
WAKE
Control
SP0
V
PWR
V
PWR
, V
DD
, 5.0 V
POR
Bandgap
Sleep PWR
VPWR
VDD
GND
2.0
mA
16.0
mA
To
+
2.0 4.0 V
–
SPI
mA Ref
Comparator
V
PWR
V
PWR
16.0
mA
2.0
mA
SP7
5.0 V
Oscillator
and
Clock Control
V
PWR
5.0 V
Temperature
Monitor and
Control
5.0 V
125 kΩ
V
PWR
V
PWR
16.0
mA
SG0
SG1
SG2
SG3
SG4
SG5
SG6
SG7
SG8
SG9
SG10
SG11
SG12
SG13
V
PWR
V
PWR
16.0
mA
2.0
mA
2.0
mA
SG0
SPI Interface
and Control
V
DD
125 kΩ
INT
INT
Control
V
DD
MUX Interface
40
μA
CS
V
DD
SCLK
SI
SO
SG13
To
+
4.0 V
–
SPI
Ref
Comparator
+
V
DD
Analog Mux
Output
–
AMUX
Figure 2. 33972 Simplified Internal Block Diagram
33972
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
