MC33910BAC / MC34910BAC
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
INTERRUPT (IRQ)
HIGH SIDE OUTPUTS (HS1 AND HS2)
The IRQ pin is a digital output used to signal events or
faults to the MCU while in Normal and Normal Request mode
or to signal a wake-up from Stop mode. This active low output
will transition to high, only after the interrupt is acknowledged
by a SPI read of the respective status bits.
These high side switches are able to drive loads such as
relays or lamps. Their structure is connected to the VS2
supply pin. The pins are short-circuit protected and also
protected against overheating.
HS1and HS2 are controlled by SPI and can respond to a
signal applied to the PWMIN input pin.
WATCHDOG CONFIGURATION (WDCONF)
The HS1 and HS2 outputs can also be used during Low
Power mode for the cyclic-sense of the wake input.
The WDCONF pin is the configuration pin for the internal
watchdog. A resistor can be connected to this pin to configure
the window watchdog period. When connected directly to
ground, the watchdog will be disabled. When this pin is left
open, the watchdog period is fixed to its lower precision
internal default value (150 ms typical).
POWER SUPPLY (VS1 AND VS2)
Those are the battery level voltage supply pins. In an
application, VS1 and VS2 pins must be protected against
reverse battery connection and negative transient voltages,
with external components. These pins sustain standard
automotive voltage conditions such as load dump at 40 V.
GROUND CONNECTION (AGND, PGND, LGND)
The AGND, PGND and LGND pins are the Analog and
Power ground pins.
The high side switches (HS1 and HS2) are supplied by the
VS2 pin, all other internal blocks are supplied by VS1 pin.
The AGND pin is the ground reference of the voltage
regulator.
VOLTAGE SENSE PIN (VSENSE)
The PGND and LGND pins are used for high current load
return as in the LIN interface pin.
This input can be connected directly to the battery line. It
is protected against battery reverse connection. The voltage
present in this input is scaled down by an internal voltage
divider, and can be routed to the ADOUT0 output pin and
used by the MCU to read the battery voltage.
Note: PGND, AGND and LGND pins must be connected
together.
DIGITAL/ANALOG (L1)
The ESD structure on this pin allows for excursion up to
+40 V, and down to -27 V, allowing this pin to be connected
directly to the battery line. It is strongly recommended to
connect a 10kohm resistor in series with this pin for protection
purposes.
The L1 pin is a multi purpose input. It can be used as a
digital input, which can be sampled by reading the SPI and
used for wake-up when 33910 is in Low Power mode or used
as analog inputs for the analog multiplexer. When used to
sense voltage outside the module, a 33kohm series resistor
must be used on each input.
HALL SENSOR SWITCHABLE SUPPLY PIN (HVDD)
When used as a wake-up input L1 can be configured to
operate in Cyclic-Sense mode. In this mode, one of the high
side switches is configured to be periodically turned on and
sample the wake-up input. If a state change is detected
between two cycles a wake-up is initiated. The 33910 can
also wake-up from Stop or Sleep by a simple state change on
L1.
This pin provides a switchable supply for external hall
sensors. While in Normal mode, this current limited output
can be controlled through the SPI.
The HVDD pin needs to be connected to an external
capacitor to stabilize the regulated output voltage.
+5V MAIN REGULATOR OUTPUT (VDD)
When used as analog input, the voltage present on the L1
pins is scaled down by an selectable internal voltage divider
and can be routed to the ADOUT0 output through the analog
multiplexer.
An external capacitor has to be placed on the VDD pin to
stabilize the regulated output voltage. The VDD pin is
intended to supply a microcontroller. The pin is current limited
against shorts to GND and over-temperature protected.
Note: If L1 input is selected in the analog multiplexer, it will
be disabled as digital input and remains disabled in low
Power mode. No wake-up feature is available in that
condition.
During Stop mode the voltage regulator does not operate
with its full drive capabilities and the output current is limited.
During Sleep mode the regulator output is completely shut
down.
When the L1 input is not selected in the analog
multiplexer, the voltage divider is disconnected from that
input.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
67
FREESCALE [ Freescale ]
