MC33910G5AC/MC3433910G5AC
FUNCTIONAL DEVICE OPERATIONS
OPERATIONAL MODES
RST Wake-up
WINDOW CLOSED
NO WATCHDOG CLEAR
ALLOWED
WINDOW OPEN
FOR WATCHDOG
CLEAR
While in Stop mode, the 33910 can wake-up when the
RST pin is held low long enough to pass the internal glitch
filter. Then, the 33910 will change to Normal Request or
Normal modes depending on the WDCONF pin
configuration. The RST wake-up does not generate an
interrupt and is not reported via SPI.
From Stop mode, the following wake-up events can be
configured:
WD TIMING X 50%
WD TIMING X 50%
• Wake-up from L1 input without cyclic sense
• Cyclic sense wake-up inputs
• Force wake-up
WD PERIOD (t
)
PWD
WD TIMING SELECTED BY RESISTOR
ON WDCONF PIN
• CS wake-up
• LIN wake-up
• RST wake-up
Figure 15. Window Watchdog Operation
To disable the watchdog function in Normal mode the user
must connect the WDCONF pin to ground. This measure
effectively disables Normal Request mode. The WDOFF bit
in the Watchdog Status Register (WDSR) will be set. This
condition is only detected during Reset mode.
From Sleep mode, the following wake-up events can be
configured:
• Wake-up from L1 input without cyclic sense
• Cyclic sense wake-up inputs
• Force wake-up
If neither a resistor nor a connection to ground is detected,
the watchdog falls back to the internal lower precision
timebase of 150 ms (typ.) and signals the faulty condition
through the Watchdog Status Register (WDSR).
• LIN wake-up
WINDOW WATCHDOG
The 33910 includes a configurable window watchdog
which is active in Normal mode. The watchdog can be
configured by an external resistor connected to the WDCONF
pin. The resistor is used to achieve higher precision in the
timebase used for the watchdog.
The watchdog timebase can be further divided by a
prescaler which can be configured by the Timing Control
Register (TIMCR). During Normal Request mode, the
window watchdog is not active but there is a 150 ms (typ.)
timeout for leaving the Normal Request mode. In case of a
timeout, the 33910 will enter into Reset mode, resetting the
microcontroller before entering again into Normal Request
mode.
SPI clears are performed by writing through the SPI in the
MOD bits of the Mode Control Register (MCR).
During the first half of the SPI timeout, watchdog clears are
not allowed, but after the first half of the SPI timeout window,
the clear operation opens. If a clear operation is performed
outside the window, the 33910 will reset the MCU, in the
same way as when the watchdog overflows.
FAULTS DETECTION MANAGEMENT
The 33910 has the capability to detect faults like an over
or under-voltage on VS1, TxD in permanent Dominant State,
Over-temperature on HS, LIN. It is able to take corrective
actions accordingly. Most of faults are monitoring through
SPI and the Interrupt pin. The microcontroller can also take
actions.
The following table summarizes all fault sources the
device is able to detect with associated conditions. The status
for a device recovery and the SPI or pins monitoring are also
described.
33910
Analog Integrated Circuit Device Data
Freescale Semiconductor
31
FREESCALE [ Freescale ]
