INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VIGNP
CRES
Charge
Pump
To Gate
Drives
M1
M3
S1
Current
Sense,
Limitation,
and Mirror
VCC
VCCL
CSNS
+3.3 V
Internal
Regulator
S0
M2
Gate
Drives
M4
PWM
Override
REDIS
LSCMP
FWD
REV
PWM
EN1
EN2
VDDQ
SCLK
CS
DI
DO
Direction
and PWM
Control
Baseline
Slew Rate
Set
RS
Command, Fault, and
Temperature Register
Temperature
Sense and
Shutdown
GND
Figure 2. 33899 Simplified Internal Block Diagram
33899
2
Analog Integrated Circuit Device Data
Freescale Semiconductor