INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
TXD
Bus DRVR
TX
BUS DRVR
MODE0
MODE1
HV WU E n
HVWU Enable
Mode
Mode
Co ntrol
Control
Wa ve Sha ping E n
Waveshaping Enable
TX Dat
Data
TXD
a
BUS
Disab le
Disable
Bus RCVR
BUS RCVR
HVWU
De t
HV WU
Detect
RX Dat a
RXD Data
Disab le
Disable
TXD
RXD
Undervoltage
Detect
Timer
OSC
Load Switch
VBATT
BAT
Timers
LOAD
GND
CNTL
CNTL*
*CNTL terminal is present on 33897/A/C/T only.
Figure 3. 33897/A/B/C/D/T Simplified Internal Block Diagram
33897/A/B/C/D/T
4
Analog Integrated Circuit Device Data
Freescale Semiconductor