INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD
__
CS
SCLK
DI
DO
OV, POR, SLEEP
~50
µA
VPWR
Overvoltage
Shutdown/POR
Sleep State
Internal
Bias
Charge
Pump
GND
EN
~50
µA
SPI and
Interface
Logic
SPI Bit 0
Typical of All 8 Output Drivers
TLIM
IN5
~50
µA
Enable
SPI Bit 4
Gate
Drive
Control
Current
Limit
Open
Load
Detect
Current
~650
µA
D1
D2
D3
D4
D7
D8
S1
S2
S3
S4
S7
S8
Drain
Outputs
IN6
~50
µA
IN5
+
–
+
–
Open/Short Comparator
+
_
~1.5 V Open/Short Threshold
Source
Outputs
TLIM
Gate
Drive
Control
Current
Limit
Open
Load
Detect
Current
~650
µA
D5
D6
Drain
Outputs
+
–
+
–
Open/Short Comparator
+
_
S5
S6
Source
Outputs
~1.5 V Open/Short Threshold
Figure 2. 33880 Simplified Internal Block Diagram
33880
2
Analog Integrated Circuit Device Data
Freescale Semiconductor