FUNCTIONAL DEVICE OPERATION
OPERATION DESCRIPTION
extends the application flexibility of the IC without having to
use an external resistor divider, thus improving the regulator
accuracy over the whole temperature range, and reducing
the component count.
In order to engage the power down sequence, the
following conditions have to be met:
(VIGN . REGON) + UVLO = Power Down
The VDD3 output is not power sequenced when used as a
standby regulator.
The status of the programming pin can be selected either
by tying the pin to ground (logic level “0”). The logic level “1”
can be selected either by tying the programming pin up (the
programming pin can be tied up to the battery voltage) or by
leaving the pin open.
SENSOR SUPPLIES (VREF1, VREF2)
There are two sensor supplies, VREF1 and VREF2,
integrated into the IC. They are internally connected to VDDH
through power MOSFETs which protect against short to
battery (up to +40V) and short to ground (down to -1V)
conditions.
The programming information is read and latched with the
500μs delay after the power is applied to the IC.
Table 6. Programming VDD3, VDDL, VKAM Output
Voltage
The VREF outputs have a linearly regulated current limit of
250mA (max.) and their own thermal protection.
V
V
V
KAM
P1
P2
P3
DD3
DDL
Severe fault conditions on the VREF1and VREF2 outputs,
like shorts to either ground or battery, will not disrupt the
operation of the main regulator VDDH, or cause assertion of
any Reset signal.
High
High
High
High
Low
Low
Low
Low
High
High
Low
Low
High
High
Low
Low
High
Low
High
Low
High
Low
High
Low
3.3V
3.3V
2.6V
3.3V
1.5V
3.3V
3.3V
3.15V
3.3V
3.3V
2.6V
3.3V
1.0V
1.0V
1.0V
5.0V
1.0V
1.5V
3.3V
IMPORTANT NOTE:
The VREF outputs MUST be externally protected against
transient voltage events with slew rates faster than
2.0V/μs, otherwise damage to the part may occur. A practical
and inexpensive solution consists of using a series RC
network connected from the VREF output to ground (see
Figures 8 and 9 for typical component values). Other means,
such as a single electrolytic capacitor with its capacitance
value C > 10μF, may be also used.
3.3V
3.3V Standby
2.0
2.6V Standby
2.6V Standby
The Programming Pins can be tied high to battery voltage
PROTECTION FET DRIVE (PFD)
LOW BATTERY OPERATION
The Protection FET Drive circuit allows using an optional
N-channel protection MOSFET (instead of a standard
reverse protection diode) to protect against a reverse battery
voltage condition. This approach improves the operating
capabilities at very low battery voltages.
When the battery voltage falls below the specified
minimum value, the 33730 switching regulator will enter a
100% duty cycle mode of operation and its output voltage
VDDH will follow the decreasing battery voltage. If the battery
voltage continues to fall, the VDDH voltage reaches its reset
threshold level, and the RSTH signal will be pulled low, but
the other linear regulators will continue to operate, and their
monitoring signals stay high as long as the VDDH provides
sufficient headroom for the regulators to stay in their
regulation limits (see Figure 6 and Figure 7). If the battery
voltage continues to fall, the linear regulators would not have
sufficient headroom to stay in regulation, and their resets
would be asserted (RSTL, RST3, or both would be pulled
low). At that moment the power down sequence would be
engaged.
An internal charge pump is used to enhance the
Protection FET gate during nominal and low battery
conditions. The charge pump will be enabled at the startup
voltage. When the battery voltage gets sufficiently high, the
Protection FET is turned off and the integrated circuit power
input (VBAT pins) are supplied through the body diode of the
Protection FET.
Use of the Protection FET is not necessary in systems
already using a protection diode, relay or when no reverse
battery protection is required.
The VKAM standby regulator will operate down to (VKAM and
VKAM_DO) and VKAM-DO at the KA_VBAT pin.
CONTROL INPUT (VIGN)
The VIGN pin is used as a control input to the IC. The
regulation circuits will function and draw current from VBAT
when VIGN is high (active) or when the REGON pin is high.
The VIGN pin has a VIHN-IH power-up threshold VIGN-IL typical
power-down threshold) and VIGN-HYS (minimum) of
hysteresis. VIGN is designed to operate up to max VBAT
battery while providing reverse battery and max VBAT load
dump protection.
POWER SEQUENCING (VDDH, VDD3, VDDL)
VDDH, VDD3, and VDDL are power sequenced by means of
internal pull-down FETs. During the power up sequence,
VDD3 and VDDL will follow VDDH
.
During the power down sequence the VDD3 and VDDL
outputs will be pulled down by the internal pull-down power
FETs, and VDDH will be shut off with a defined delay (~100μs
typ.).
33730
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
FREESCALE [ Freescale ]
