ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
ELECTRICAL PERFORMANCE CURVES
t
R(SI)
V
DD
= 5.0 V
t
F(SI)
< 50 ns
< 50 ns
0.7 V
DD
5.0 V
50%
0.2 V
DD
0.7 V
DD
t
R(SO)
t
F(SO)
SCLK
0
V
OH
V
OL
V
OH
t
DLY(LH)
SCLK
33291L
Under
Test
SO
C
L
= 200 pF
SO
(Low-to-High)
0.2 V
DD
SO
(High-to-Low)
t
VALID
0.7 V
DD
t
DLY(HL)
C
L
represents the total capacitance of the test fixture and probe.
0.2 V
DD
V
OL
SO (Low-to-High) is for an output with internal conditions such that
the low-to-high transition of
CS
causes the SO output to switch from
high to low.
Figure 4. Valid Data Delay Time and
Valid Time Test Circuit
Figure 6. Valid Data Delay Time and
Valid Time Waveforms
t
R(SI)
V
DD
= 5.0 V
V
Pull-Up
= 2.5 V
t
F(SI)
< 50 ns
0.7
VDD
5.0 V
0
CS
0.2 VDD
< 50 ns
90%
10%
tSO(EN)
90%
R
L
= 1.0 kΩ
SO
(High-to-Low)
tSO(DIS)
VTri-State
CS
33291L
Under
Test
SO
C
L
= 20 pF
tSO(EN)
90%
10%
tSO(DIS)
tSO(dis
VOH
SO
(Low-to-High)
10%
VTri-State
C
L
represents the total capacitance of the test fixture and probe.
Figure 5. Enable and Disable Time Test Circuit
1. SO (high-to-low) waveform is for SO output with internal conditions such
that SO output is low except when an output is disabled as a result of de-
tecting a circuit fault with CS in a High Logic state; e.g., open load.
2. SO (low-to-high) waveform is for SO output with internal conditions such
that SO output is high except when an output is disabled as a result of de-
tecting a circuit fault with CS in a High Logic state; e.g., shortened load.
Figure 7. Enable and Disable Time Waveforms
33291L
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
