PIN CONNECTIONS
PIN CONNECTIONS
PIN ASSIGNMENT
VBAT
VBAT
OUT1
OUT1
VBAT
VBAT
NC
IN1
ST1
OLDE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VBAT
VBAT
OUT2
OUT2
VBAT
VBAT
NC
IN2
ST2
GND
Figure 2. 33289 Pin Connections
Table 1. Pin Function Description
Pin Number
1, 2, 5, 6, 15, 16,
19, 20
Pin Name
VBAT
Pin Function
Supply Voltage
Definition
These are the power supply pins of the device. These pins are directly connected
with the lead frame of the package and are tied to the drain of the switching
MOSFET. These pins can be directly connected to the battery voltage. In addition
to their supply function, these pins participate to the thermal behavior of the
device in conducting the heat from the switching MOSFET to the printed circuit
board.
Pins 3 and 4 are the output 1 pins. Pins 17 and 18 are the output 2 pins. They are
directly connected to the source of the power MOSFET. These pins are used by
the control circuitry to sense the device output voltage. The R
DSON
is 40 mΩ max
per output at 25°C and will increase to a maximum of 75 mΩ at 150°C junction
temperature.
These are the device input pins which directly control their associated outputs.
The levels are CMOS compatible. When the input is a logic low, the associated
output MOSFET is in the off state. When input is high, the MOSFET is turned on
and the load is activated.
When both inputs are low, the device is in standby mode and its supply current is
reduced. Each input pin has an internal active pull down, so that it will not float if
disconnected.
9, 12
ST1
ST2
Status for Channel 1
Status for Channel 2
These pins are the channel 1 and channel 2 fault detection flags. Their internal
structure is an open drain architecture with an internal clamp at 6.0 V. An external
pull up resistor connected to V
DD
(5.0 V) is needed. This is an active low output.
If the device is in its normal condition the status lines will be high. If open load or
other fault occurs, the associated channel status flag will be pulled low. See
Functional Truth Table.
This pin is a digital input which enables the open load current diagnostic circuitry.
When OLDE is a logic low, the open load circuitry is not powered and the device’s
bias current draw is at a minimum. If OLDE is a logic high, the open load circuitry
is functional at the price of a higher bias current draw. OLDE pin has a pull down
resistor.
This is the GND pin of the device.
3, 4, 18, 17
OUT1
OUT2
OUTPUT Channel 1
OUTPUT Channel 2
8, 13
IN1
IN2
INPUT Channel 1
INPUT Channel 2
10
OLDE
Open Load Detection
Enable
11
GND
GROUND
33289
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
