FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The power FETs are turned ON by charging their gate
capacities with a current flowing out of pins OUT1 and OUT2.
During PWM, the values of table below are guaranteed. They
are measured with 8.0 nF on OUT1 and 16 nF on OUT2. Test
condition VIN: ramp 0 V ≤ 2.5 V or 2.5 V ≤ 5.0 V.
5.0 V
IN
THRIN2
IN
2.5 V
THRIN1
V
OUT1
V
CCP
V
+ 7.0
VCC
V
OUT2
V
OUT2
20 ms
5.0 V
2.5 V
2.5 V
IN
IN
0 V
V
OUT2MAX
V
OUT1MAX
V
OUT2
0 V
V
OUT1
0
ON1
0 V
t
t
ON3
t
ON2
0
t
ON3
t
t
ON1 ON2
MINIMUM V
1, OUT2
= 100 µSEC
MINIMUM V
1,OUT2
= 1.0 µSEC
MINIMUM V
1,OUT2
OUT
= 1.5 µSEC
OUT
OUT
VOLTAGE V
VCC
AFTER T
AFTER T
AFTER T
ON1
ON2
ON3
7.0 V < V
10 V < V
20 V < V
< 10 V
< 20 V
< 40 V
V
V
V
- 0.7 V
- 0.7 V
- 0.7 V
V
V
+ 5.95 V
+ 9.35 V
V
VCC
+ 7.0 V
+ 11 V
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
V
VCC
Figure 4. Turn On Behavior
Turn Off Characteristics
The output voltages at OUT1 and OUT2 are limited by
controlling the current sources ION1, ION2 to avoid current
flowing through the external or the internal zener diode.
The power FETs on OUT1 and OUT2 are turned OFF by
discharging the gate capacity with the constant discharge
current IOUTOFF
• Discharge current IOUTxOFF is IOUTxOFF = 110 µA
condition: VOUT x > 0.5 V ( VIN < VTHRxIN
.
When voltage power supply plus threshold voltage
(VCC + VTH) is reached, the current sources are turned OFF.
)
• Threshold VTH1 for OUT1 output voltage control is
7.0 V < VTH1 < VZ
• Threshold VTH2 for OUT2 output voltage control is
7.0 V < VTH2 < 15 V
• Test conditions for switching OFF the power FETs:
1. IN open
2. Stages disabled via pin IN
3. Stage OUT1 disabled by an over current error
33285
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
FREESCALE [ Freescale ]
