FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
CFP AND CFM
Accumulated current filter cap plus and minus terminals respectively. The coulomb counter will require a 10 µF output
capacitor connected between these pins to perform a first order filtering of the signal across R1.
CHRGSE1B
An unregulated wall charger configuration can be built in which case this pin must be pulled low. When charging through USB,
it can be left open since it is internally pulled up to VCORE. The recommendation is to place an external FET that can pull it low
or left it open, depending on the charge method.
CHRGLED
Trickle LED driver output 1. Since normal LED control via the SPI bus is not always possible in the standalone operation, a
current sink is provided at the CHRGLED pin. This LED is to be connected between this pin and CHRGRAW.
GNDCHRG
Ground for charger interface.
LEDR, LEDG AND LEDB
General purpose LED driver output Red, Green and Blue respectively. Each channel provides flexible LED intensity control.
These pins can also be used as general purpose open drain outputs for logic signaling, or as generic PWM generator outputs.
GNDLED
Ground for LED drivers
IC CORE
VCORE
Regulated supply output for the IC analog core circuitry. It is used to define the PUMS VIH level during initialization. The
bandgap and the rest of the core circuitry are supplied from VCORE. Place a 2.2 μF capacitor from this pin to GNDCORE.
VCOREDIG
Regulated supply output for the IC digital core circuitry. No external DC loading is allowed on VCOREDIG. VCOREDIG is kept
powered as long as there is a valid supply and/or coin cell. Place a 2.2 μF capacitor from this pin to GNDCORE.
REFCORE
Main bandgap reference. All regulators use the main bandgap as the reference. The main bandgap is bypassed with a
capacitor at REFCORE. No external DC loading is allowed on REFCORE. Place a 100 nF capacitor from this pin to GNDCORE.
GNDCORE
Ground for the IC core circuitry.
POWER GATING
PWGTDRV1 AND PWGTDRV2
Power Gate Drivers.
PWGTDRV1 is provided for power gating peripheral loads sharing the processor core supply domain(s) SW1, and/or SW2,
and/or SW3. In addition, PWGTDRV2 provides support to power gate peripheral loads on the SW4 supply domain.
In typical applications, SW1, SW2, and SW3 will both be kept active for the processor modules in state retention, and SW4
retained for the external memory in self refresh mode. SW1, SW2, and SW3 power gating FET drive would typically be connected
to PWGTDRV1 (for parallel NMOS switches). SW4 power gating FET drive would typically be connected to PWGTDRV2. When
low power Off mode is activated, the power gate drive circuitry will be disabled, turning off the NMOS power gate switches to
isolate the maintained supply domains from any peripheral loading.
13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
33
FREESCALE [ Freescale ]
