SPI BITMAP
The 24 bit wide registers are numbered from 0 to 63, and are referenced throughout this document by register number, or
representative name as given in the corresponding captions. The contents of all registers are given in the tables defined in this
chapter; each table includes the following information:
Name: Name of the bit. Spare bits are implemented in the design for future use, but are not assigned. Unused bits are not
available in the design. Reserved bits are not implemented in the design, but are used on other PMIC's.
Bit #: The bit location in the register (0-23)
R/W: Read / Write access and control
• R is read access
• W is write access
• R/W is read and write access
• RW1C is read and write access with write 1 to clear
• RWM is read and write access while the device can modify the bit
Reset: Resetting signal
• RESETB, which is the same signal as the RESETB pin (so bit is held in reset as long as RESETB is low)
• RTCPORB which is the reset signal of the RTC module (so bit is no longer held in reset once RTC power is good)
• OFFB which is an internal signal generated when transitioning into the Off state
• NONE. There is no reset signal for hardwired bits nor for the bits of which the state is determined by the power up mode
settings
Default: The value after reset as noted in the Default column of the SPI map.
• Fixed defaults are explicitly declared as 0 or 1.
• * corresponds to Read / Write bits that are initialized at startup based on power up mode settings (board level pin
connections) validated at the beginning of Cold or Warm Start. Bits are subsequently SPI modifiable.
• S corresponds to Read only sense bits that continuously monitor an input signal (sense signal is not latched).
• L corresponds to Read only sense bits that are latched at startup.
• X indicates that the state does not have an explicitly defined default value which can be specified. For instance, some bits
default to a value which is dependent on the version of the IC.
Description: A short description of the bit function, in some cases additional information is included
The following tables are intended to give a summarized overview, for details on the bit description, see the individual chapters.
Table 112. Register 0, Interrupt Status 0
Name
ADCDONEI
Bit #
R/W
Reset
Default
Description
0
1
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
RW1C
R
RESETB
RESETB
RESETB
OFFB
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADC has finished requested conversions
ADCBIS has finished requested conversions
Touch screen wake-up
ADCBISDONEI
TSI
2
VBUSVALIDI
IDFACTORYI
USBOVI
3
VBUSVALID detect
4
RESETB
RTCPORB
OFFB
ID factory mode detect
5
USB over-voltage detection
Charger attach
CHGDETI
CHGFAULTI
CHGREVI
CHGSHORTI
CCCVI
6
7
RTCPORB
RESETB
RESETB
RESETB
RESETB
OFFB
Charger fault detection
8
Charger path reverse current
Charger path short circuit
Charger path CC / CV transition detect
Charge current below threshold warning
BP turn on threshold
9
10
11
12
13
14
15
16
17
18
19
20
CHGCURRI
BPONI
LOBATLI
RESETB
RESETB
Low battery low threshold warning
Low battery high threshold warning
For future use
LOBATHI
Reserved
BVALIDI
RW1C
R
OFFB
USB B-session valid interrupt
For future use
Reserved
Reserved
IDFLOATI
IDGNDI
R
For future use
RW1C
RW1C
RESETB
RESETB
USB ID float detect
USB ID ground detect
13892
Analog Integrated Circuit Device Data
Freescale Semiconductor
122
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