5.0V, HcMOS SMD Oscillator
with Standby
Model: F4101 SERiES
Page 1 of 2
RoHS compliant / Pb Free
Rev. 1/23/2009
FEATURES
•
•
•
•
5.0V Operation
HCMOS Output
Standby Function
Tape and Reel
(2,000 pcs. STD)
7 .5 M ax
Top
View
• PART nUMbER SElEcTiOn
Part Number
118-Frequency-xxxxx
119-Frequency-xxxxx
120-Frequency-xxxxx
121-Frequency-xxxxx
122-Frequency-xxxxx
123-Frequency-xxxxx
446-Frequency-xxxxx
Frequency
Model
Number Stability
1
±100PPM
F4101
F4101R
±100PPM
±50PPM
F4102
±50PPM
F4102R
±25PPM
F4103
F4103R*
±25PPM
±20PPM
F4104*
Operating
Temperature
-10 ~ +70ºC
-40 ~ +85ºC
-10 ~ +70ºC
-40 ~ +85ºC
-10 ~ +70ºC
-40 ~ +85ºC
-10 ~ +70ºC
Frequency
Range (MHz)
0.012 ~ 170.000
0.012 ~ 170.000
0.012 ~ 170.000
0.012 ~ 170.000
0.012 ~ 162.000
0.012 ~ 156.250
0.012 ~ 162.000
#4
#1
Dot denotes
pin 1
#3
5 .2 M ax
#2
1 .5 M ax
1 .4 ±0.2
Bottom
View
• ElEcTRicAl cHARAcTERiSTicS
PARAMETERS
Frequency Range (F
o
)
Storage Temperature Range (T
stg
)
Supply Voltage
(V
dd
)
Input Current
(I
dd
)
0.012 ~ 32.000 MHz
32.000+ ~ 67.000 MHz
67.000+ ~ 125.000 MHz
125.000+ ~ 170.000 MHz
Output Symmetry (50% V
dd
)
Rise Time (10% ~ 90% V
dd
) (T
r
)
0.012 ~ 79.999999 MHz
80.000 ~ 170.000 MHz
Fall Time (90% ~ 10% V
dd
) (T
f
)
0.012 ~ 79.999999 MHz
80.000 ~ 170.000 MHz
Output Voltage
(V
ol
)
(V
oh
)
Output Current
(I
ol
)
(I
oh
)
Output Load
(HCMOS)
Standby Current
Start-up Time
(T
s
)
Output Disable Time
2
Output Enable Time
2
1
MAX
(unless otherwise noted)
0.012 ~ 170.000 MHz
-55ºC ~ +125ºC
5.0V ± 10%
18mA
50mA
80mA
90mA
40% ~ 60%
5nS
4nS
5nS
4nS
10% V
dd
90% V
dd
Min
2mA Min
-2mA Min
15pF
10µA
10mS
150nS
10mS
#1
#4
#2
#3
5 .0 8 ±0.1
2 .6 ±0.2
Recommended
Solder Pad Layout
1 .8 ±0.1
2 .0 ±0.1
4 .2 ±0.1
5 .0 8 ±0.1
Pin Connections
# 1 E /D
#3 O u tp u t
# 2 G N D #4 V
DD
A ll d im e n sio n s a re in m illim eters
Inclusive of 25ºC tolerance, operating temperature range, input voltage change, load change, ag-
ing, shock, and vibration. *Excludes shock/vibration.
2
An internal pullup resistor from pin 1 to pin 4 allows active output if pin 1 is left open.
Note: A 0.01µF bypass capacitor should be placed between VDD (Pin 4) and GND (Pin 2) to
minimize power supply line noise.
Drawing is for reference to critical specifications defined by size measurements.
Certain non-critical visual attributes, such as side castellations, reference pin shape, etc. may
vary. All specifications subject to change without notice.
• EnAblE / DiSAblE FUncTiOn
OUTPUT (Pin 3)
INH (Pin 1)
ACTIVE
OPEN
2
ACTIVE
'1' Level V
ih
≥
70% V
dd
High Z
'0' Level V
il
≤
30% V
dd
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71
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