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FSP2114 参数 Datasheet PDF下载

FSP2114图片预览
型号: FSP2114
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS低压降稳压器 [CMOS LOW DROPOUT REGULATORS]
分类和应用: 稳压器
文件页数/大小: 8 页 / 334 K
品牌: FOSLINK [ FOSLINK SEMICONDUCTOR CO.,LTD ]
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CMOS LOW DROPOUT REGULATORS
FUNCTIONAL BLOCK DIAGRAM
FSP2114
IN
CURRENT
SENSE
OUT
THERMAL
SHUTDOWN
REFERENCE
& BIAS
G
FUNCTIONAL DESCRIPTION
The FSP2114 is a high performance LDO with low quiescent current consumption. As illustrated in the above Figure,
Functional Block Diagram, the FSP2114 architecture incorporates reference and bias circuitry, error amplifier,
feedback voltage resistor divider, 2Ω P-channel power MOSFET pass transistor and current limiter.
VOLTAGE REGULATION
Normally, the LDO's error amplifier compares the output feedback voltage (via the resistor divider) with the reference
voltage and generates an error signal that is used to drive the P-channel power MOSFET. When the output voltage
is higher than the needed value, the P-channel is driven to maintain regulation. When the output voltage is lower
than the needed value, the P-channel conducts to increase the output to its desired value. This negative feedback
mechanism results in a constant regulated output voltage.
CURRENT LIMIT
When the output current is at the current limit value, the current limiter circuitry prevents the output current from
increasing further. This current limit value is typically 400mA for output voltage higher than 2V, and decreases for
lower output voltage parts (see Typical Performance Characteristics). As the output voltage decreases, the current
limit value folds back gradually, eventually reaching 100mA at 0V.
APPLICATION INFORMATION
INPUT CAPACITOR
Any good quality capacitor with a value of 1µF or more can be used as an input capacitor for this LDO. Connect the
input capacitor as close to the IN and G as possible. Ceramic capacitors have better performance and lower ESR
(Equivalent Series Resistance) than other types of capacitors, and are recommended.
OUTPUT CAPACITOR
The
FSP2114 LDO requires an output capacitor for stability. This capacitor should be connected as close to OUT
and G as possible to maximize the performance of the device. The output capacitance and ESR ranges for stability
are shown in the Region of Stable C
OUT
ESR vs. Output Current graph in Typical Performance Characteristics.
However, to ensure the best performance for the device, the output capacitor should have a minimum capacitance of
1µF, and an ESR value between 10mΩ and 500mΩ. High quality ceramic capacitors with X7R or X5R dielectric
types are strongly recommended.
3/8
2007-5-18