F81866A
5
4
3
2
1
0
RI1_WAKEUP_EN
Reserved
R/W VBAT
R/W VBAT
R/W VBAT
R/W VBAT
R/W VBAT
R/W VBAT
0
0
0
0
0
0
Set this bit to enable RI1# event to wakeup system.
Reserved
GP_WAKEUP_EN
TMOUT_WAKEUP_EN
MO_WAKEUP_EN
KB_WAKEUP_EN
Set this bit to enable GPIO event to wakeup system.
Set this bit to enable Timeout event to wakeup system.
Set this bit to enable Mouse event to wakeup system.
Set this bit to enable Keyboard event to wakeup system.
7.9.23ERP Deep S3 Delay Register ⎯ Index E9h
Bit
Name
R/W
Default
Description
Reset
The delay time from S3 state to deep S3 state. The unit is 64ms and
default is 1.024 sec.
7-0
DS3_DELAY_TIME
R/W VBAT
Fh
7.9.24ERP Mode Select Register ⎯ Index ECh
Bit
Name
R/W
Default
Description
Reset
00: Fintek G3’ mode.
01: Intel DSW + Fintek G3` mode.
10: Reserved.
7-6
ERP_MODE
R/W VBAT
0
11: Intel DSW mode.
5
4
DPWROK_CTRL_EN
SOFT_START_EN
R/W VBAT
R/W VBAT
0
1
Set “1” to enable DPWROK reset by ERP_CTRL1#.
0: disable ERP soft start.
1: enable ERP soft start.
The soft start rate.
00: 5ms.
3-2
1-0
SOFT_START_RATE
Reserved
R/W VBAT
1h
-
01: 10ms.
10: 27ms.
11: 54ms.
-
-
Reserved
7.9.25ERP WDT Control Register ⎯ Index EDh
Bit
Name
R/W
Default
Description
Reset
Time of ERP watchdog timer.
7-6
ERP_WD_TIME[11:10]
R/W
-
VBAT
Write index EEh will load watchdog time.
7-5
4
Reserved
R
R
-
-
-
-
Reserved
ERP_WDTMOUT_STATUS
ERP_WD_TIME[9:8]
VBAT
Watchdog timeout status.
Reserved
3-2
R/W VBAT
R/W VBAT
R/W VBAT
ERP WDT unit. It is the time unit of ERP_WD_TIME.
0: 1sec.
1
0
WD_UNIT
WD_EN
0
0
1: 60 sec.
Set “1” to enable ERP WDT. Auto clear if timeout occurred.
177
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
