F81866A
7.7.11.1GPIO7 Output Enable Register ⎯ Index 80h
Bit
Name
R/W Reset Default
Description
0: GPIO77 is in input mode.
1: GPIO77 is in output mode.
7
GPIO77_OE
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
0
0
0
0
0
0
0
0
0: GPIO76 is in input mode.
1: GPIO75 is in output mode.
6
5
4
3
2
1
0
GPIO76_OE
GPIO75_OE
GPIO74_OE
GPIO73_OE
GPIO72_OE
GPIO71_OE
GPIO70_OE
0: GPIO75 is in input mode.
1: GPIO75 is in output mode.
0: GPIO74 is in input mode.
1: GPIO74 is in output mode.
0: GPIO73 is in input mode.
1: GPIO73 is in output mode.
0: GPIO72 is in input mode.
1: GPIO72 is in output mode.
0: GPIO71 is in input mode.
1: GPIO71 is in output mode.
0: GPIO70 is in input mode.
1: GPIO70 is in output mode.
7.7.11.2GPIO7 Output Data Register ⎯ Index 81h (This byte could be also written by base address + 3)
Bit
Name
R/W Reset Default
Description
0: GPIO77 outputs 0 when in output mode.
1: GPIO77 outputs 1 when in output mode.
7
GPIO77_VAL
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
R/W LRESET#
1
1
1
1
1
1
1
1
0: GPIO76 outputs 0 when in output mode.
1: GPIO76 outputs 1 when in output mode.
6
5
4
3
2
1
0
GPIO76_VAL
GPIO75_VAL
GPIO74_VAL
GPIO73_VAL
GPIO72_VAL
GPIO71_VAL
GPIO70_VAL
0: GPIO75 outputs 0 when in output mode.
1: GPIO75 outputs 1 when in output mode.
0: GPIO74 outputs 0 when in output mode.
1: GPIO74 outputs 1 when in output mode.
0: GPIO73 outputs 0 when in output mode.
1: GPIO73 outputs 1 when in output mode.
0: GPIO72 outputs 0 when in output mode.
1: GPIO72 outputs 1 when in output mode.
0: GPIO71 outputs 0 when in output mode.
1: GPIO71 outputs 1 when in output mode.
0: GPIO70 outputs 0 when in output mode.
1: GPIO70 outputs 1 when in output mode.
7.7.11.3GPIO7 Pin Status Register ⎯ Index 82h (This byte could be also read by base address + 3)
Bit
7
Name
R/W Reset Default
Description
The pin status of GPIO77/STB#.
GPIO77_IN
GPIO76_IN
GPIO75_IN
R
R
R
-
-
-
-
-
-
6
The pin status of GPIO76/AFD#.
The pin status of GPIO75/ERR#.
5
162
Jan, 2012
V0. 12P