F81866A
7.7.3.2GPIO IRQ Sharing Mode Register ꢀ Index 7Fh
Bit
Name
R/W
Default
Description
Reset
GPIO8 IRQ sharing mode:
00 : Sharing IRQ active low Level.
01 : Sharing IRQ active high edge.
10 : Sharing IRQ active high Level.
11 : Reserved.
7-6
GP8_IRQ_MODE
R/W
0
LRESET#
This bit is effective when IRQ is sharing with other device
(GP8_IRQ_SHARE is “1”).
GPIO5 IRQ sharing mode:
00 : Sharing IRQ active low Level.
01 : Sharing IRQ active high edge.
10 : Sharing IRQ active high Level.
11 : Reserved.
LRESET#
LRESET#
LRESET#
5-4
3-2
1-0
GP5_IRQ_MODE
GP1_IRQ_MODE
GP0_IRQ_MODE
R/W
R/W
R/W
0
0
0
This bit is effective when IRQ is sharing with other device
(GP5_IRQ_SHARE is “1”).
GPIO1 IRQ sharing mode:
00 : Sharing IRQ active low Level.
01 : Sharing IRQ active high edge.
10 : Sharing IRQ active high Level.
11 : Reserved.
This bit is effective when IRQ is sharing with other device
(GP1_IRQ_SHARE is “1”).
GPIO0 IRQ sharing mode:
00 : Sharing IRQ active low Level.
01 : Sharing IRQ active high edge.
10 : Sharing IRQ active high Level.
11 : Reserved.
This bit is effective when IRQ is sharing with other device
(GP0_IRQ_SHARE is “1”).
7.7.4.GPIO0x Configuration Registers
Register
Default Value
MSB
Register Name
0x[HEX]
LSB
F0
GPIO0 Output Enable Register
GPIO0 Output Data Register
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
F1
1
141
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
