F81867
The three bits {LED_VCC_S0_MODE_ADD, LED_VCC_S0_MODE [1:0]}
select the LED_VCC mode in S0 state.
000: Sink low.
001: Tri-state or drive high control by GPIO11_DRV_EN.
010: 0.5Hz clock with 50% duty.
011: 1Hz clock with 50% duty.
1-0
LED_VCC_S0_MODE R/W VBAT
00
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.*
111: 0.25Hz clock with 25% duty.*
*When LED_VCC_INV_DIS is set to “1” the duty is 25%, otherwise, the duty
is 75%.
LED Control Register 2 ⎯ Index F9h
Reset
Bit
7
Name
R/W
Default
Description
-
Reserved
-
-
Reserved
VBAT
VBAT
VBAT
-
Refer to LED_VSB_S5_MODE.
Refer to LED_VSB_S3_MODE.
Refer to LED_VSB_S0_MODE.
6
LED_VSB_S5_MODE_ADD R/W
LED_VSB_S3_MODE_ADD R/W
LED_VSB_S0_MODE_ADD R/W
0
0
0
-
5
4
3
Reserved
-
Reserved
VBAT
VBAT
VBAT
Refer to LED_VCC_S5_MODE.
2
LED_VCC_S5_MODE_ADD R/W
LED_VCC_S3_MODE_ADD R/W
LED_VCC_S0_MODE_ADD R/W
0
0
0
Refer to LED_VCC_S3_MODE.
Refer to LED_VCC_S0_MODE.
1
0
LED Control Register 3 ⎯ Index FAh
Bit
Name
R/W
Default
Description
Reset
7
Reserved
-
-
-
Reserved
0: Disable LED_VSB deep S3 mode.
6
LED_VSB_DS3
R/W VBAT
0
1: Enable LED_VSB deep S3 mode. Output 0.25HZ clock with 25% duty.
The three bits {LED_VSB_S5_MODE_ADD, LED_VSB_S5_MODE [1:0]}
select the LED_VSB mode in S5 state.
000: Sink low.
001: Tri-state or drive high control by GPIO10_DRV_EN.
010: 0.5Hz clock with 50% duty.
011: 1Hz clock with 50% duty.
5-4
LED_VSB_S5_MODE R/W VBAT
00
100: 0.125Hz clock with 50% duty.
101: 0.25Hz clock with 50% duty.
110: 0.125Hz clock with 25% duty.*
111: 0.25Hz clock with 25% duty.*
182
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
