F81867
7. Register Description
The configuration register is used to control the behavior of the corresponding devices. To configure the register,
using the index port to select the index and then writing data port to alter the parameters. The default index port and
data port are 0x4E and 0x4F respectively. Pull down the RTS1# pin to change the default value to 0x2E/0x2F. To
enable configuration, the entry key 0x87 must be written to the index port. To disable configuration, write exit key 0xAA
to the index port. Following is an example to enable configuration and disable configuration by using debug.
-o 4e 87
-o 4e 87
-o 4e aa
( enable configuration )
( disable configuration )
The Following is a register map (total devices) grouped in hexadecimal address order, which shows a summary of
all registers and their default value. Please refer to each device chapter if you want more detail information.
Global Control Registers
“-“ Reserved or Tri-State
Global Control Registers
Register
0x[HEX]
Default Value
Register Name
Software Reset Register
MSB
LSB
02
-
-
-
-
0
-
-
-
0
0
0
0
1
0
0
1
0
07
Logic Device Number Register (LDN)
Chip ID Register
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
-
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
-
20*
21*
23*
24*
25*
26*
27*
1
Chip ID Register
1
Vendor ID Register
1
Vendor ID Register
1
I2C Address Register
Clock Select Register
Port Select Register
0
0
1/0 1/0
0
1/0
28*
28*
29*
Multi Function Select 1 Register
Multi Function Select 2 Register
Multi Function Select 3 Register
-
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
29*
2A*
2B*
2B*
2C*
2C*
10Hz Clock Divisor High Byte
10Hz Clock Divisor Low Byte
0
1
0
-
0
1
0
-
0
1
0
-
0
0
-
0
0
-
0
1
-
1
1
1
-
1
1
0
-
Multi Function Select 4 Register
10Hz Fine Tune Clock Count High Byte
10Hz Fine Tune Clock Count Low Byte
GPIO0 Enable Register
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
119
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
