F81867
TSI Temperature 2 Low Byte – Index E2h
Bit
Name
R/W
Reset Default
Description
This is the low byte of Intel temperature interface CPU reading. The
reading is the fraction part of CPU temperature. Bit 0 indicates the error
status.
TSI_TEMP2_LO
R
5VSB
5VSB
-
0: No error.
1: Error code.
7-0
To access this byte, MCH_BANK_SEL should be set to “0”.
This is the 12th byte of the block read protocol.
This byte is also used as the 3rd byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
I2C_DATA2
R/W
8’h00
TSI Temperature 2 High Byte – Index E3h
Bit
Name
R/W
Reset Default
Description
This is the high byte of Intel temperature interface CPU reading. The
reading is the decimal part of CPU temperature.
TSI_TEMP2_HI
R
5VSB
5VSB
-
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
This is the 13th byte of the block read protocol.
I2C_DATA3
R/W
This byte is also used as the 4th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
8’h00
TSI Temperature 3 – Index E4h
Bit
Name
R/W
Reset Default
Description
This is the high byte of Intel temperature interface MCH reading. The
range is 0~255ºC.
TSI_TEMP3
R
5VSB
5VSB
-
To access this byte, MCH_BANK_SEL should be set to “0”.
7-0
This is the 14th byte of the block read protocol.
I2C_DATA4
R/W
This byte is also used as the 5th byte of block write protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
8’h00
TSI Temperature 4 – Index E5h
Bit
Name
R/W
Reset Default
Description
This is the high byte of Intel temperature interface DIMM0 reading. The
range is 0~255ºC.
7-0
TSI_TEMP4
R
5VSB
-
To access this byte, MCH_BANK_SEL should be set to “0”.
50
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
