F81866A
6.6.2.7
6.6.2.8
6.6.2.9
6.7
GPIO6x ...................................................................................................................92
GPIO7x ...................................................................................................................93
GPIO8x ...................................................................................................................93
Watchdog Timer Function .......................................................................................93
ACPI Function.........................................................................................................94
Power Control.............................................................................................................95
Wake Up Via Sleep State........................................................................................95
Wake Up Stage Detection.......................................................................................95
AC Loss & Resume Control Methods .....................................................................96
Intel Power Saving Function Deep Sleep Well (DSW) ...............................................97
Power Saving Controller (Fintek ERP Mode).............................................................99
ACPI Timing .............................................................................................................103
G3 To S0 ...............................................................................................................103
G3 To S0 (only DSW)............................................................................................104
G3 To S0 (DSW & ERP, AC Resume Green Bold Line)........................................105
DSW To S0............................................................................................................106
S0 to DSW ............................................................................................................107
S0 to G3’...............................................................................................................108
PWOK Signals..........................................................................................................109
6.8
6.8.1
6.8.1.1
6.8.1.2
6.8.1.3
6.8.2
6.8.3
6.8.4
6.8.4.1
6.8.4.2
6.8.4.3
6.8.4.4
6.8.4.5
6.8.4.6
6.8.5
6.9 UART………….....................................................................................................................109
6.9.1
6.9.2
UART Device Register..........................................................................................109
Programmable Baud Rate..................................................................................... 113
6.10 AMD TSI and Intel PECI 3.0 Functions................................................................................ 114
6.11 Over Voltage Protection ....................................................................................................... 115
Register Description ................................................................................................... 116
7.
7.1
7.2
Global Control Registers...................................................................................................... 116
Multifunction Function Register Mapping Table ...................................................................124
Multi Function Register Mapping For FDC...............................................................124
Multi Function Register Mapping For Parallel Port (LPT).........................................125
Multi Function Register Mapping For Hardware Monitor..........................................125
Multi Function Register Mapping For KBC (PS/2 Mouse)........................................126
Multi Function Register Mapping For GPIO0x..........................................................126
Multi Function Register Mapping For GPIO1x..........................................................126
Multi Function Register Mapping For GPIO2x..........................................................127
Multi Function Register Mapping For GPIO3x..........................................................127
Multi Function Register Mapping For GPIO4x..........................................................128
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
Multi Function Register Mapping For GPIO5x..........................................................128
Jan, 2012
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
