F81866A
0 : No transmission delay when SIR is changed from RX to TX.
2
TXW4C_IR
R/W LRESET#
0
1 : Transmission delay 4 character-time when SIR is changed from RX to TX.
IRQ_MODE1 and IRQ_MODE0 will select the UART5 interrupt mode if IRQ
sharing is enabled.
00 : Sharing IRQ active low Level mode.
01 : Sharing IRQ active high edge mode.
10 : Sharing IRQ active high Level mode.
1
0
IRQ_MODE0
IRQ_SHARE
R/W LRESET#
0
0
11 : Reserved.
This bit is effective at IRQ is sharing with the other device (IRQ_SHARE, bit 1).
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
R/W LRESET#
7.15.6IR Mode Select Register ⎯ Index F1h
Bit
Name
R/W Reset Default
Description
7-5
Reserved
-
-
-
Reserved. Return 010b when read.
0X: Disable IR1 function.
10 : Enable IR1 function, active pulse is 1.6uS.
IRMODE1
IRMODE0
4-3
2
R/W LRESET#
R/W LRESET#
00b
11 : Enable IR1 function, active pulse is 3/16 bit time.
0 : Full Duplex function for IR self test.
1 : Half Duplex function.
HDUPLX
1
Return 1 when read.
0 : IRTX is not inversed.
1 : Inverse the IRTX.
1
0
TXINV_IR
RXINV_IR
R/W LRESET#
R/W LRESET#
0
0
0 : IRRX is not inversed.
1 : Inverse the IRRX.
7.15.7Clock Register ⎯ Index F2h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
-
Reserved.
Select the clock source for UART6.
00: 1.8432MHz.
1-0
UART6_CLK_SEL R/W LRESET# 00b 01: 18.432MHz.
10: 24MHz.
11: 14.769MHz.
194
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
