F81485
3
Pin Configuration
F81485
RO
RE
DE
1
2
3
R
8
Vcc
B
7
6
5
A
DI 4
D
GND
4
Pin Description
INt
O4
- TTL level input pin.
- Output pin with 4mA driver.
P
- Power.
4.1. Power Pin
Type
Description
Pin
Pin Name
5
8
GND
VCC
P
P
GND.
4.75V< VCC < 5.25V power supply voltage input.
4.2. Transceiver
Pin
Pin Name
Type
Description
Receiver Output. When enabled (RE# is low), then if
A > B by 200 mV, RO is high.
1
RO
O4
A < B by 200 mV, RO is low.
Active Low Receiver Output Enable pin.
A low level enables the receiver output, RO.
A high level places it in a high impedance state.
Active High Driver Output Enable.
A high level enables the driver differential outputs, A and
B. The chip will function as a line driver.
A low level places it in a high impedance state. The chip
will function as a line receiver.
2
3
RE#
INt
INt
DE
5
Jan, 2012
V0.11P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
