F81218
10. Application Circuit
(Power On Setting Pin)
VCC3V
VCC3V
RI5#
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10 R11 R12 R13
DCD5#
SOUT5
SIN5
PIN_67
4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
C1
0.1U
DTR5#
RTS5#
DSR5#
CTS5#
PIN_73
PIN_74
PIN_52
CTS2#
U1
R1 on: UART
R7 on: UART
R3 on: UART
R6 on: UART
6
5
4
3
addr:0x238 IRQ11/F; off:UART
addr:0x338 IRQ10/E; off:UART
6
5
disabled.
disabled.
DSR2#
RTS2#
DTR2#
SIN2
SOUT2
DCD2#
RI2#
RI3#
DCD3#
SOUT3
SIN3
DTR3#
RTS3#
DSR3#
CTS3#
PIN_76
PIN_50
PIN_49
addr:0x2e8 IRQ9; off:UART
addr:0x3e8 IRQ5; off:UART
4
3
disabled.
disabled.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
SOUT2
DCD2#
RI2#
IRRX2
IRTX2
CTS1#
DSR1#
RTS1#
DTR1#
SIN1
SOUT1
DCD1#
RI1#
IRRX1
IRTX1
GP25
GP24
GP23
GP22
GP21
GP20
ADD_DEC0#
ADD_DEC1#
IRQA
DTR3#
RTS3#
DSR3#
CTS3#
GP14
GP15
GP16
RI4#
DCD4#
SOUT4
SIN4
DTR4#
RTS4#
DSR4#
CTS4#
RI6#
DCD6#
SOUT6
SIN6
DTR6#
RTS6#
DSR6#
CTS6#
CLKIN
D0
R10 on
:
UART
2
addr:0x2f8 irq4; R9 on and R10 off: UART
disabled.
2
addr:0x2e0 IRQ4;
1 addr:0x3e0 IRQ3;
R9 off and R10 off:UART
2
CTS1#
DSR1#
RTS1#
DTR1#
SIN1
SOUT1
DCD1#
RI1#
PIN_83
PIN_84
R13 on
:
UART
1
addr:0x3f8 irq3; R12 on and R13 off: UART
disabled.
RI4#
R12 off and R13 off:UART
1
DCD4#
SOUT4
SIN4
DTR4#
RTS4#
DSR4#
CTS4#
RI6#
DCD6#
SOUT6
SIN6
DTR6#
RTS6#
DSR6#
CTS6#
PIN_41
PIN_39
PIN_86
R5 on: Watch Dog Timer enabled and setting to 10 second when the clock input
is 24Mhz. If the clock input is 48Mhz
off :disabled.
,
the timer is setting to
5
second.
F81218D
IRRX
IRTX
R2 On:LPC interface; Off:ISA intreface
PIN_33
R8
0
R4
0
R11
0
Address
Entry Key
0x77
On:1
IRQB
0x4e/0x4f
0x2e/0x2f
0x4e/0x4f
0x2e/0x2f
0x4e/0x4f
0x2e/0x2f
0x4e/0x4f
0x2e/0x2f
Off:0
VCC3V
VSB3V
0
0
1
0x77
R14 R15
8.2K 4.7K
R16
10K
VCC3V
VCC3V
0
1
0
0xa0
0
1
1
0xa0
C2
0.1U
PCIRST#
PME#
WDT_OUT#
LAD3
LAD2
LAD1
LAD0
PCICLK
LFRAME#
SERIRQ
CLK24IN
1
0
0
0x87
1
0
1
0x87
1
1
0
0x67
1
1
1
0x67
Title
Feature Integration Technology Inc.
Size
B
Document Number
F81218D f or LPC
Rev
0.2
Date:
Tuesday, September 16, 2003
Sheet
1
of
2
-54-
August, 2007
V0.33P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
