F81218
Table of Content
1. General Description ......................................................................................................................................... 1
2. Feature List ...................................................................................................................................................... 1
3. Pin Configuration............................................................................................................................................. 2
4. Pin Description................................................................................................................................................. 3
4.1 ISA/LPC Interface ................................................................................................................................. 3
4.2 UART Interface...................................................................................................................................... 5
4.3 GPIO pins............................................................................................................................................. 10
4.4 Power ................................................................................................................................................... 10
5. Functional Description................................................................................................................................... 11
5.1 LPC Interface.................................................................................................................................... 11
5.2 UART................................................................................................................................................ 11
5.3 IR Function ....................................................................................................................................... 16
5.4 Watch Dog Timer Function............................................................................................................... 17
5.5 Serial IRQ ......................................................................................................................................... 18
6. Register Description................................................................................................................................... 20
6.1 Global Control Register.................................................................................................................... 23
6.1.1 Software Reset Register – index 02h........................................................................................ 23
6.1.2 Logic Device Select Register – index 07h................................................................................ 24
6.1.3 Device ID Register– index 20h, 21h......................................................................................... 24
6.1.4 Vendor ID Register– index 23h, 24h......................................................................................... 24
6.1.5 Clock Source Select Register – index 25h................................................................................ 24
6.1.6 GPIO Function Select Register ( ISA Interface Only ) – index 26h......................................... 25
6.1.7 Test Mode Register – index 2Fh ............................................................................................... 25
6.2 UART 1 Device Control Register (LDN 0) ......................................................................................... 26
6.2.1
6.2.2
6.2.3
Device Enable Register – index 30h.................................................................................. 26
I/O Port Select Register – index 60h.................................................................................. 26
I/O Port Select Register – index 61h.................................................................................. 26
6.2.4 IRQ Channel Select Register – index 70h ............................................................................. 26
6.2.5 UART 1 Clock Select Register – index F0h .......................................................................... 27
6.2.6 IR1 Control Register – index F1h.......................................................................................... 28
6.3 UART 2 Device Control Register (LDN 1) ......................................................................................... 28
6.3.1
6.3.2
6.3.3
Device Enable Register – index 30h.................................................................................. 28
I/O Port Select Register – index 60h.................................................................................. 28
I/O Port Select Register – index 61h.................................................................................. 29
6.3.4 IRQ Channel Select Register – index 70h ............................................................................. 29
F81218
August, 2007
V0.33P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
