F81216
Table of Content
1. General Description.......................................................................................................................................1
2. Feature List....................................................................................................................................................1
3. Pin Configuration ..........................................................................................................................................2
4. Pin Description..............................................................................................................................................3
4.1 ISA/LPC Interface ..................................................................................................................................3
4.2 UART Interface.......................................................................................................................................4
4.3 Power ......................................................................................................................................................7
5. Functional Description ..................................................................................................................................8
5.1 LPC Interface.......................................................................................................................................8
5.2 UART...................................................................................................................................................8
5.2.1 UART Port Register.....................................................................................................................9
5.3 IR Function ........................................................................................................................................13
5.4 Watch Dog Timer Function................................................................................................................13
5.4.1 Watchdog Port Register ..........................................................................................................14
5.5 Serial IRQ ..........................................................................................................................................14
5.5.1 Start Frame.................................................................................................................................15
5.5.2 IRQ/Data Frame.........................................................................................................................15
5.5.3 Stop Frame.................................................................................................................................16
6.
Register Description............................................................................................................................16
6.1 Global Control Register.....................................................................................................................19
6.1.1 Software Reset Register – index 02h.........................................................................................19
6.1.2 Logic Device Select Register – index 07h.................................................................................19
6.1.3 Device ID Register– index 20h, 21h..........................................................................................19
6.1.4 Vendor ID Register– index 23h, 24h..........................................................................................19
6.1.5 Clock Source Select Register – index 25h.................................................................................20
6.1.6 Test Mode Register – index 2Fh ................................................................................................20
6.2 UART 1 Device Control Register (LDN 0) ..........................................................................................20
6.2.1
6.2.2
6.2.3
Device Enable Register – index 30h...................................................................................20
I/O Port Select Register – index 60h...................................................................................20
I/O Port Select Register – index 61h...................................................................................21
6.2.4 IRQ Channel Select Register – index 70h ..............................................................................21
6.2.5 UART 1 Clock Select Register – index F0h ...........................................................................21
6.2.6 IR1 Control Register – index F1h...........................................................................................22
6.3 UART 2 Device Control Register (LDN 1) ..........................................................................................22
6.3.1
Device Enable Register – index 30h...................................................................................22
F81216.
August, 2007
V0.32P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
