F75223
6. Pin Description
I
Input, 5V tolerance
INst,5v
O
TTL level input pin and schmitt trigger, 5V tolerance.
Output, 5V tolerance
O16
OD12,5v
Output pin with 16 mA sink capability.
Open drain, 12mA sink capability, 5V tolerance
TTL level bi-directional pin and schmitt trigger,Open-drain output with 12 mA source-sink capability,
5V tolerance.
Power pin
II/OD12st,5v
P
Power Pin
Pin No.
Pin Name
GND
Type
P
Description
Ground.
2
3
VSB
P
3V power.
3V power
18
VBAT
P
SMBUS Interface
Pin No.
13
Pin Name
Type
PWR
Description
SMCLK
SMBUS clock.
SMBUS data.
I/OD12st,5v VSB
I/OD12st,5v VSB
SMDAT
14
Host SPI Interface
Pin No.
Pin Name
Type
PWR
VSB
VSB
VSB
VSB
Description
HCS#
SPI chip select from Master.
I
I
I
4
5
6
7
HCLK
Master SPI clock.
HMOSI
HMISO
Master data out and slave data input.
Master data in and slave data out.
O
Slave SPI Interface
Pin No.
Pin Name
Type
PWR
Description
MISO
I
Master data input and slave data output.(Bypass Mode)
Master data input and slave data output.(Refresh Mode)
Master data output and slave data input.(Bypass Mode)
Master data output and slave data input with 16 mA sink
capability.(Refresh Mode)
8
VSB
INst,5v
O
MOSI
9
VSB
O16
CLK
O
O16
O
Slave SPI clock.(Bypass Mode)
10
11
12
VSB
VSB
VSB
Slave SPI clock with 16 mA sink capability.(Refresh Mode)
SPI chip select 1.(Bypass Mode)
CS1#
CS2#
O16
O
SPI chip select 1 with 16 mA sink capability. (Refresh Mode)
SPI chip select 2.(Bypass Mode)
O16
SPI chip select 2 with 16 mA sink capability. (Refresh Mode)
7
Jan., 2012
V0.16P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
