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F75121RG 参数 Datasheet PDF下载

F75121RG图片预览
型号: F75121RG
PDF下载: 下载PDF文件 查看货源
内容描述: 动态VID控制+ 8 GPIO数据表 [Dynamic VID Control + 8 GPIO Datasheet]
分类和应用:
文件页数/大小: 45 页 / 937 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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I2C_ADDR  
INtsd100k  
The GPIO serial bus hardware power on  
setting pin. Default address is 0x9C  
(when I2C_ADDR=0). Another one is  
0x6E (when I2C_ADDR=1). This pin  
internal pull-down 100k to Ground. If this  
pin is pull-up 10k to VSB3V, this pin will  
be trapped to 1.  
13  
14  
15  
SDATA  
SCLK  
I/OD12ts  
INts  
VSB3V  
VSB3V  
VSB3V  
SMbus data.  
SMBus clock  
RSTOUT#  
OD12  
System reset signal when the Reset-Out  
timer is time out. This pin will generate  
100mS pulse when the Reset-Out timer  
is timeout.  
17  
SLOTOCC#  
VIDOUT[0:5]  
INts  
VBAT  
Powered by VBAT. CPU detect pin.  
CPU Voltage ID output.  
24,23,22,21,  
20,19  
OD16  
VSB3V  
28  
SEL  
INtsd100k  
VSB3V  
VSB3V  
Default pull up to 3VSB.  
General purpose I/O pins.  
2,27,26,25  
GPIO30,GPIO31, I/OD12ts  
GPIO32,GPIO33  
6. Functional Description  
6.1 General Description  
The F75121 provides VIDIN, VIDOUT function. It can latch the VIDIN from CPU side, and output VIDOUT to  
PWM. The VIDOUT value can be programmed by the interface GPIO Serial Bus serial interface.  
Dedicate GPIO functions. That includes two set watchdog timer. The watchdog timer timeout unit is set to second  
and range is 0 to 31 seconds. When the timeout has occurred, that will generate a status bit to indicate it and write  
one will be clear.  
All GPIO can be programmed to logic one or zero or high pulse or low pulse.  
- 7 -  
July, 2007  
V0.24P