F75111
0
1
7
8
0
7
8
SCL
SDA
0
0
1
1
1
0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Start By
Master
Ack
by
111
Stop by
Master
Ack
by
111
Frame 1
Serial Bus Address Byte
Frame 2
Internal Index Register Byte
0
Figure 2. Serial Bus Write to Internal Address Register Only
(c) Serial bus read from a register with the internal address register prefer to desired location
0
7
8
0
7
8
SCL
SDA
1
0
0
1
1
1
0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Start By
Master
Ack
by
Master
Ack
by
111
Stop by
Master
Frame 1
Serial Bus Address Byte
Frame 2
Internal Index Register Byte
0
Figure 3. Serial Bus Read from Internal Address Register
7. Registers Description
7.1 Configuration and Control Register – Index 01h
Power-on default [7:0] =0000_1000b
Bit
Name
R/W
PWR
Description
7
INIT
R/W
VSB3V Software reset for all registers including Test Mode registers. Users use
only.
6
5
Reserved
R/W
R/W
VSB3V
EN_WDT10
VSB3V Enable Reset Out. If set to 1, enable WDTOUT10# output. Default is
disable.
4
3
2
1
Reserved
Reserved
Reserved
SMART_POW
R_MANAGEM
ENT
R/W
R/W
R/W
R/W
VSB3V
VSB3V
VSB3V
VSB3V Set this bit to 1 will enable auto power down mode, when all function are
idle then 20ms the chip will auto power down, it will wakeup when GPIO
state change or read write register
0
SOFT_POWR_ R/W
DOWN
VSB3V Set this bit to 1 will power down all of the analog block and stop internal
clock, write 0 to clear this bit or when GPIO state change will auto clear
this bit to 0.
- 9 -
July, 2007
V0.27P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
