F75113
Indicate GPIO21 Edge Status. If set to 1, the edge of GPIO21
1
0
STS_GP21EDGE
STS_GP20EDGE
R
R
-
-
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
Indicate GPIO20 Edge Status. If set to 1, the edge of GPIO20
has occurred. Write 1 to clear this bit. Writing 0 is invalid.
8.2.52 GPIO2X SMI Enable Register ⎯ Index 3Ah
Bit
Name
R/W Default
Description
Enable GPIO27 SMI Generation. If this bit set to 1, enable
GPIO27 to generate SMI.
7
EN_GP27SMI
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Enable GPIO26 SMI Generation. If this bit set to 1, enable
GPIO26 to generate SMI.
6
5
4
3
2
1
0
EN_GP26SMI
EN_GP25SMI
EN_GP24SMI
EN_GP23SMI
EN_GP22SMI
EN_GP21SMI
EN_GP20SMI
Enable GPIO25 SMI Generation. If this bit set to 1, enable
GPIO25 to generate SMI.
Enable GPIO24 SMI Generation. If this bit set to 1, enable
GPIO24 to generate SMI.
Enable GPIO23 SMI Generation. If this bit set to 1, enable
GPIO23 to generate SMI.
Enable GPIO22 SMI Generation. If this bit set to 1, enable
GPIO22 to generate SMI.
Enable GPIO21 SMI Generation. If this bit set to 1, enable
GPIO21 to generate SMI.
Enable GPIO20 SMI Generation. If this bit set to 1, enable
GPIO20 to generate SMI.
8.2.53 GPIO2X Output Driving Enable Register ⎯ Index 3Bh
Bit
Name
R/W Default
Description
Enable GPIO27 drive high buffer. If this bit is set to 0, the pin
GPIO27 will be I/OD pin, if set to 1 the pin GPIO27 is I/O pin.
7
EN_GP27_OBUF R/W
EN_GP26_OBUF R/W
EN_GP25_OBUF R/W
0
0
0
Enable GPIO26 drive high buffer. If this bit is set to 0, the pin
GPIO26 will be I/OD pin, if set to 1 the pin GPIO26 is I/O pin.
6
5
Enable GPIO25 drive high buffer. If this bit is set to 0, the pin
GPIO25 will be I/OD pin, if set to 1 the pin GPIO25 is I/O pin.
- 50 -
Dec,2011
V0.13P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
