F75113
8.2.33 GPIO4X Input Status Register ⎯ Index 72h
Bit
7
Name
R/W Default
Description
Read the GPIO47 data on the pin.
GP47_ PSTS
GP46_ PSTS
GP45_ PSTS
GP44_ PSTS
GP43_ PSTS
GP42_ PSTS
GP41_ PSTS
GP40_PSTS
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
6
Read the GPIO46 data on the pin.
Read the GPIO45 data on the pin.
Read the GPIO44 data on the pin.
Read the GPIO43 data on the pin.
Read the GPIO42 data on the pin.
Read the GPIO41 data on the pin.
Read the GPIO40 data on the pin.
5
4
3
2
1
0
8.2.34 GPIO4X Level/Pulse Control Register ⎯ Index 73h
Name R/W Default
Bit
7
Description
GPIO47 output mode. 0 – level, 1 – pulse.
GPIO46 output mode. 0 – level, 1 – pulse.
GPIO45 output mode. 0 – level, 1 – pulse.
GPIO44 output mode. 0 – level, 1 – pulse.
GPIO43 output mode. 0 – level, 1 – pulse.
GPIO42 output mode. 0 – level, 1 – pulse.
GPIO41 output mode. 0 – level, 1 – pulse.
GPIO40 output mode. 0 – level, 1 – pulse.
GP47_ OMODE R/W
GP46_ OMODE R/W
GP45_ OMODE R/W
GP44_ OMODE R/W
GP43_ OMODE R/W
GP42_ OMODE R/W
GP41_ OMODE R/W
GP40_ OMODE R/W
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
8.2.35 GPIO4X Pulse Width Control Register ⎯ Index 74h
Bit
Name
R/W Default
Description
7-2
Reserved
-
-
Reserved
GPIO4x pulse width. If set the GPIO4x to pulse mode, the pulse
width can be defined as follows.
00b – 500us (Default)
01b – 1ms
1-0
GP4_PLSWD
R/W
0
10b – 20ms
11b – 100ms
- 69 -
Dec,2011
V0.13P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
