F75113
1b: Enable SIRQ function of GPIO4X port.
0b: Disable SIRQ function of GPIO4X port.
4
3
2
1
0
SERIRQ4_EN
SERIRQ3_EN
SERIRQ2_EN
SERIRQ1_EN
SERIRQ0_EN
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
1b: Enable SIRQ function of GPIO3X port.
0b: Disable SIRQ function of GPIO3X port.
1b: Enable SIRQ function of GPIO2X port.
0b: Disable SIRQ function of GPIO2X port.
1b: Enable SIRQ function of GPIO1X port.
0b: Disable SIRQ function of GPIO1X port.
1b: Enable SIRQ function of GPIO0X port.
0b: Disable SIRQ function of GPIO0X port.
8.2.18 SIRQ Channel Select0 Register ⎯ Index 52h
Name R/W Default
Bit
Description
The register would select SIRQ channel of GPIO1X port.
7-4
SIRQCH_SEL1 R/W
SIRQCH_SEL0 R/W
0
0
The register would select SIRQ channel of GPIO0X port.
3-0
8.2.19 SIRQ Channel Select1 Register ⎯ Index 53h
Name R/W Default
Bit
Description
The register would select SIRQ channel of GPIO3X port.
7-4
SIRQCH_SEL3 R/W
SIRQCH_SEL2 R/W
0
0
The register would select SIRQ channel of GPIO2X port.
3-0
8.2.20 SIRQ Channel Select2 Register ⎯ Index 54h
Name R/W Default
Bit
Description
0b: SIRQ function is active high.
7
SIRQ_ACTL_EN R/W
0
1b: SIRQ function is active low.
Reserved
6-4
3-0
Reserved
-
-
The register would select SIRQ channel of GPIO4X port.
SIRQCH_SEL4 R/W
0
- 62 -
Dec,2011
V0.13P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
